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参数资料
| 型号： | MC144144P |
| 厂商： | MOTOROLA INC |
| 元件分类： | 颜色信号转换 |
| 英文描述： | Digital Signal Processors 44-JLCC -55 to 125 |
| 中文描述： | COLOR SIGNAL DECODER, PDIP18 |
| 封装： | PLASTIC, DIP-18 |
| 文件页数： | 37/44页 |
| 文件大小： | 565K |
| 代理商： | MC144144P |
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MC144144
37
MOTOROLA
SDA (Pin 14)
When the serial control port has been set to I2C mode
operation, this pin serves as the bidirectional data line for
sending and receiving serial data. In SPI mode operation it
operates as serial data input. SPI mode output data is avail-
able on the SDO pin.
OUTPUTS
SDO (Pin 16)
Provides the serial data output when SPI mode commu-
nications have been selected. This pin is not used in I2C
mode operation.
BOX (Pin 17)
Black box keying output. This active HIGH, CMOS level
signal is used to key in the black box in the captions/text dis-
plays. This output will be in the high–impedance state when
the background attribute has been set to semi–transparent.
RED, GREEN, BLUE (Pins 18, 2, 3)
Positive acting, CMOS levels signals.
Color Mode:
Red, green, and blue character video out-
puts for use in a color receiver.
Mono Mode:
All three outputs carry the character lumi-
nance information.
EXTERNAL COMPONENTS
CSYNC (Pin 8)
Sync slice level. A 0.1
μ
F capacitor must be tied between
this pin and analog ground (VSS(A)). This capacitor stores
the sync slice level voltage.
LPF (Pin 9)
Loop filter. A series RC low–pass filter must be tied be-
tween this pin and analog ground (VSS(A)). There must also
be a second capacitor from the pin to VSS(A). Values for the
three parts to be specified.
RREF (Pin 10)
Reference setting resistor. Must be a 10 k
, 2% resistor.
POWER SUPPLY
VDD (Pin 12)
The voltage on this pin is nominally 5.0 V and may range
between 4.75 to 5.25 V with respect to the VSS pins.
VSS (Pins 1 and 11)
These pins are the lowest potential power pins for the ana-
log and digital circuits. They are normally tied to system
ground.
The recommended printed circuit pattern for implementing
the power connection and critical components will be sup-
plied at a later date.
APPLICATIONS INFORMATION
PCB DESIGN
To maximize the performance of the MC144144, noise
should be kept to a minimum. Good printed circuit board de-
sign will enhance the operation of the MC144144. Separate
analog and digital grounds will reduce noise and decoding
errors. In addition, separate filters on VDD(A) and VDD(D)
will also help to minimize noise and decoding errors. Suffi-
cient decoupling and short leads will also improve perfor-
mance.
When designing mixed analog/digital printed circuit
boards, separate ground planes for digital ground and analog
ground should be employed. Large switching currents gener-
ated by digital circuits will be amplified by analog circuitry
and can quickly make a circuit unusable. Digital oscillators
can become a source of EMI (electromagnetic interference)
problems. Care should be taken to ensure analog ground
does not inadvertently become part of the digital ground. The
analog and digital grounds should be connected together at
only one point. This should be the VDD(A) and VDD(D) pins
on the MC144144 if possible. Additionally, when intercon-
necting several printed circuit boards together, care must be
taken to ensure cabling does not interconnect digital and
analog grounds together to produce a path for digital switch-
ing currents through analog ground.
When using any device that combines digital and analog
circuitry, such as the MC144144, ground planes are desir-
able. Loosely interconnected traces and/or random areas of
ground strewn around the printed circuit board are inade-
quate for high performance circuitry. While distribution of
VDD(A) and VDD(D) can be done by bussing, to do so with
the ground system is disastrous. Stray ground inductance
can increase radiation and make EMI suppression very diffi-
cult.
A 1–inch long conductor is an 18 nH inductor. The cross
sectional area of the conductor affects the exact value of the
inductance, but for most PCB traces this is approximately
correct. If the ground system is composed of traces or
clumps of ground loosely interconnected, it will be inductive.
The amount of inductance will be proportional to the length of
the conductors making up the ground. This inductance can-
not be decoupled away. It must be designed out.
A CMOS device exhibits a characteristic input capacitance
of about 10 pF. If this gate is driven by a digital signal that
switches 2.5 V in a period of 5 ns, the equation for the aver-
age current flowing during the switching time will be:
IAV = Cdv/dt.
A voltage change of 2.5 V in 5 ns requires an average cur-
rent of 5 mA. If we assume a linear ramp starting from zero,
the total change in current will be 10 mA. The change in cur-
rent per nanosecond per gate can be found by dividing the
change in current by the time
10 mA/5 ns = 2 mA/ns.
For a device with outputs driving one gate for each output,
di/dt = 16 x 2 mA/ns = 32 mA/ns.
If the above 1–inch wire is in this current path, then the
voltage dropped across it can be found from the formula
v = Ldi/dt = 18 nH x 32 mA/ns = 0.576 V.
If the inductor is in the ground system, it is in the signal
path. The voltage generated by the switching currents
through this inductor will be added to the signal. At best it will
be superimposed on the analog signal as unwanted noise. At
worst, it can render the entire circuit unusable. Even the digi-
tal signal path is not immune to this type of signal. It can false
trigger clock circuits causing timing errors, confuse compara-
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