- 您现在的位置：买卖IC网 > PDF目录371012 > MC144144P (MOTOROLA INC) Digital Signal Processors 44-JLCC -55 to 125 PDF资料下载
参数资料
| 型号： | MC144144P |
| 厂商： | MOTOROLA INC |
| 元件分类： | 颜色信号转换 |
| 英文描述： | Digital Signal Processors 44-JLCC -55 to 125 |
| 中文描述： | COLOR SIGNAL DECODER, PDIP18 |
| 封装： | PLASTIC, DIP-18 |
| 文件页数： | 8/44页 |
| 文件大小： | 565K |
| 代理商： | MC144144P |
第1页第2页第3页第4页第5页第6页第7页当前第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页第39页第40页第41页第42页第43页第44页
MC144144
8
MOTOROLA
When used, INTRO can be enabled to interrupt on selected
events.
When SEN pin is made LOW the part will be reset.
SPI Mode
SPI mode is selected by making the SMS pin HIGH.
Acts as a slave device.
All communications are clocked in and out as 8–bit bytes.
SCK is the serial clock (input), SDA is Data In, and SDO is
data out.
SEN pin enables communication. When it is LOW the SDO
pin is three–state.
When SEN is brought HIGH the part will be synchronized
and waiting for a command.
If SEN is tied HIGH, the part can be synchronized by a
command string.
When used, INTRO can be enabled to interrupt on selected
events.
When SEN and SMS pins are made LOW the part will be
reset.
Setup and Operational Control
User Selectable Displays are:
Captions, Language I, Field 1 (CC1)
Captions, Language II, Field 1 (CC2)
Captions, Language I, Field 2 (CC3)
Captions, Language II, Field 2 (CC4)
Text, Language I, Field 1 (T1)
Text, Language II, Field 1 (T2)
Text, Language I, Field 2 (T3)
Text, Language II, Field 2 (T4)
XDSG Display Mode
XDSF Display Mode
OSD mode (through the serial port)
User Controlled Features are:
Decoder ON/OFF
Color or Monochrome Output
EIA–608 Extended Attributes ON/OFF
OSD Drop Shadow ON/OFF
Text box size, Number of rows = x
Text box position, Base row = y
TV lines per character row, 13 or 15
Erase Timer (16 s) ON/OFF
Data Output Modes (through the serial port)
XDS Data Output, Raw or Filtered
Selected Channel and XDS Activity Indicators
Video Lock Indicator
Setup Options:
Horizontal timing of BOX
NTSC or PAL H lock source, Video or EXT HIN
V lock source, Video or EXT VIN
Default Condition Following Reset
Display Channel = CC1
Decoder = OFF
TEXT Size = 15 Rows
Lines/Row = 13
Background = BOX
Extended Attrib = ON
Data Outputs = OFF
NTSC operation
VCO Lock = Video
BOX Timing = 13.5
μ
s
Vert Lock = Video
VIN/INTRO = INTRO and Disabled
Horiz Lock = Video
Color/Mono = Color
OSD Display = Drop Shadow
OSD Display = 15 Lines/Row
OVERVIEW OF THE LINE 21
CLOSED CAPTION SYSTEM
THE LINE 21 CLOSED–CAPTIONING SYSTEM
The Line 21 closed–captioning system provides for the
transmission of caption information and other text material as
an encoded composite data signal during the unblanked por-
tion of Line 21, field 1 of the standard NTSC video signal. In
addition, a framing code is transmitted during the first half of
Line 21, field 2.
The encoded composite video signal for Line 21, fields 1
and 2 is shown in Figure 5. The video signal conforms to the
standard synchronizing waveform for color transmission giv-
en in Sub–part E, Part 73 of the FCC Rules and Regulations.
Multiplexed Data Channels
The Line 21, field 1 closed–caption system defines four dif-
ferent data channels which can be time multiplexed within
the Line 21 data stream. They are Captions — Language 1,
Captions — Language 2, Text — Language 1, and Text —
Language 2. Both languages may be English in either case.
Field 2 has five additional data channels, two Captions,
two Text, and Extended Data Services (XDS). The XDS data
structure is defined in EIA–608.
DATA FORMAT
The composite data signal contained within the active por-
tion of the VBI line consists of a seven–cycle sine–wave
clock run–in burst, a start bit, and 16 bits of data. These 16
bits consist of two 8–bit alphanumeric characters formulated
according to the USA Standard Code for Information Inter-
change (USASCII;x3.4–1967) with odd parity. The clock rate
is 0.5035 MHz which is 32 x FH. The clock burst and data
packet are 50 IRE units peak–to–peak and are filtered to a
“2T” response. Data is sent with the least significant bit (bit
b0) being sent first and the most significant bit (bit b7, the
parity bit) being sent last.
相关PDF资料 |
PDF描述 |
|---|---|
| MC14415DW | Digital Signal Processors 40-CDIP SB -55 to 125 |
| MC14415FL | Quad Precision Timer/Driver |
| MC14415FP | Quad Precision Timer/Driver |
| MC14415VL | Digital Signal Processors 68-CPGA -55 to 125 |
| MC14415VP | Digital Signal Processors 68-LCCC -55 to 125 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| MC14415FP | 制造商:Motorola Inc 功能描述: |
| MC14416P | 制造商:Motorola Inc 功能描述: 制造商:Motorola Inc 功能描述:TIME-SLOT ASSIGNER, 22 Pin, Plastic, DIP |
| MC14419P | 制造商:Motorola Inc 功能描述:ENCODER, 16 Pin, Plastic, DIP |
| MC14433P | 制造商:Motorola Inc 功能描述: |
| MC1443G | 制造商:Motorola Inc 功能描述: |
发布紧急采购，3分钟左右您将得到回复。