参数资料
| 型号： | MC34708VM |
| 厂商： | Freescale Semiconductor |
| 文件页数： | 33/159页 |
| 文件大小： | 0K |
| 描述： | IC POWER MANAGEMENT 206MAPBGA |
| 标准包装： | 160 |
| 应用： | 通用 |
| 电源电压： | 1.8 V ~ 4.5 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 206-LFBGA |
| 供应商设备封装： | 206-MAPBGA（13x13） |
| 包装： | 托盘 |
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Functional Block Description
7.4
7.4.1
Interrupt Management
Control
The system is informed about important events, based on interrupts. Unmasked interrupt events are signaled to the processor
by driving the INT pin high; this is true whether the communication interface is configured for SPI or I 2 C.
Each interrupt is latched so even if the interrupt source becomes inactive, the interrupt will remain set until cleared. Each interrupt
can be cleared by writing a 1 to the appropriate bit in the Interrupt Status register, which will also cause the interrupt line to go
low. If a new interrupt occurs while the processor clears an existing interrupt bit, the interrupt line will remain high.
Each interrupt can be masked by setting the corresponding mask bit to a 1. As a result, when a masked interrupt bit goes high,
the interrupt line will not go high. A masked interrupt can still be read from the Interrupt Status register. This gives the processor
the option of polling for status from the IC. The IC powers up with all interrupts masked, so the processor must initially poll the
device to determine if any interrupts are active. Alternatively, the processor can unmask the interrupt bits of interest. If a masked
interrupt bit was already high, the interrupt line will go high after unmasking.
The sense registers contain status and input sense bits, so the system processor can poll the current state of interrupt sources.
They are read only, and not latched or clearable.
Interrupts generated by external events are debounced. Therefore, the event needs to be stable throughout the debounce period
before an interrupt is generated. Nominal debounce periods for each event are documented in the INT summary table later in
this section. Due to the asynchronous nature of the debounce timer, the effective debounce time can vary slightly.
7.4.2
Interrupt Bit Summary
Table 21 summarizes all interrupt, mask, and sense bits associated with INT control. For more detailed behavioral descriptions,
refer to the related chapters.
Table 21. Interrupt, Mask and Sense Bits
Interrupt
ADCDONEI
TSDONEI
TSPENDET
USBOVP
LOWBATT
USBDET
Stuck_Key_RCV
Stuck_Key
Mask
ADCDONEM
TSDONEM
TSPENDETM
USBOVPM
LOWBATTM
USBDETM
Stuck_Key_RCV_m
Stuck_Key_m
Sense
-
-
-
USBOVPS
-
USBDETS
-
-
Purpose
ADC has finished requested conversions
Touch screen has finished conversion
Touch screen pen detect
VBUS over-voltage
Sense is 1 if above threshold.
Low battery detect
Sense is 1 if below LOWBAT threshold
USB VBUS detect
Sense is 1 if detected
Stuck key has recovered
Stuck key detected
Trigger
L2H
L2H
Dual
Dual
H2L
Dual
L2H
L2H
Debounce
Time
0
0
1.0 ms
Programmable
SUP_OVP_DB
Programmable
VBATTDB
Programmable
VBUSDB
ADC result changed
ADC_Change
ADC_Change_m
ADC_STATUS
Sense is 1 if conversion is completed, 0 if L2H
in progress
Unknown_Atta
LKR
LKP
KP
Detach
Unknown_Atta_m
LKR_m
LKP_m
KP_m
Detach_m
-
-
-
-
-
Unknown accessory detected
Remote control long key is released
Remote control long key is pressed
Remote control key is pressed
Accessory detached
L2H
L2H
L2H
L2H
L2H
MC34708
Analog Integrated Circuit Device Data ?
33
Freescale Semiconductor
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