参数资料
| 型号： | MC34708VM |
| 厂商： | Freescale Semiconductor |
| 文件页数： | 62/159页 |
| 文件大小： | 0K |
| 描述： | IC POWER MANAGEMENT 206MAPBGA |
| 标准包装： | 160 |
| 应用： | 通用 |
| 电源电压： | 1.8 V ~ 4.5 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 206-LFBGA |
| 供应商设备封装： | 206-MAPBGA（13x13） |
| 包装： | 托盘 |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页第39页第40页第41页第42页第43页第44页第45页第46页第47页第48页第49页第50页第51页第52页第53页第54页第55页第56页第57页第58页第59页第60页第61页当前第62页第63页第64页第65页第66页第67页第68页第69页第70页第71页第72页第73页第74页第75页第76页第77页第78页第79页第80页第81页第82页第83页第84页第85页第86页第87页第88页第89页第90页第91页第92页第93页第94页第95页第96页第97页第98页第99页第100页第101页第102页第103页第104页第105页第106页第107页第108页第109页第110页第111页第112页第113页第114页第115页第116页第117页第118页第119页第120页第121页第122页第123页第124页第125页第126页第127页第128页第129页第130页第131页第132页第133页第134页第135页第136页第137页第138页第139页第140页第141页第142页第143页第144页第145页第146页第147页第148页第149页第150页第151页第152页第153页第154页第155页第156页第157页第158页第159页
Functional Block Description
7.5.4.8
Dynamic Voltage Scaling
To reduce overall power consumption, processor core voltages can be varied depending on the mode or activity level of the
processor. SW1A/B and SW2 allow for two different set points with controlled transitions to avoid sudden output voltage changes,
which could cause logic disruptions on their loads.
Preset operating points for SW1A/B and SW2 can be set up for:
? Normal operation: output value selected by SPI bits SWx[5:0]. Voltage transitions initiated by SPI writes to SWx[5:0] are
governed by the DVS stepping rate shown in the following tables.
? Standby (Deep Sleep): can be higher or lower than normal operation, but is typically selected to be the lowest state retention
voltage of a given process. Set by SPI bits SWxSTBY[5:0] and controlled by a Standby event. Voltage transitions initiated by
The following table summarizes the set point control and DVS time stepping applied to SW1A/B and SW2.
Table 49. DVS Control Logic Table for SW1A/B and SW2
STANDBY
0
1
Set Point Selected by
SWx[4:0]
SWxSTBY[4:0]
Table 50. DVS Speed Selection
SWxDVSSPEED[1:0]
00
01 (default)
10
11
Function
12.5 mV step each 2.0 ? s
12.5 mV step each 4.0 ? s
12.5 mV step each 8.0 ? s
12.5 mV step each 16.0 ? s
The regulators have a strong sourcing and sinking capability in the PWM mode. Therefore, the rising/falling slope is determined
by the regulator in PWM mode, however, if the regulators are programmed in PFM or APS mode during a DVS transition, the
falling slope can be influenced by the load. Additionally, as the current capability in PFM mode is reduced, controlled DVS
transitions in PFM mode could be affected. Critically timed DVS transitions are best assured with PWM mode operation.
Voltage transitions programmed through SPI(SWx[4:0]) on SW3 and SW5 will step in increments of 25 mV per 4.0 ? s, SW4A/B
will step in increments of 25 mV per 8.0 ? s when SW4xHI[1:0]=00, and SW4A/B will step in increments of 25 mV per 16 ? s when
SW4xHI[1:0]=00. Additionally, SW3, SW4/B, and SW5 include standby mode set point programmability.
The following diagram shows the general behavior for the switching regulators when initiated with SPI programming or standby
control.
SW1 and SW2 also contain power good outputs to the application processor. The power good signal is an active high signal.
When SWxPWGD is high, it means the regulator’s output has reached its programmed voltage. The SWxPWGD voltage outputs
will be low during the DVS period and if the current limit is reached on the switching regulator. During the DVS period, the over-
current condition on the switching regulator should be masked. If the current limit is reached outside of a DVS period, the
SWxPWGD pin will stay low until the current limit condition is removed.
MC34708
Analog Integrated Circuit Device Data ?
Freescale Semiconductor
62
相关PDF资料 |
PDF描述 |
|---|---|
| MC34710EWR2 | IC PWR SUPPLY ADJ DUAL SW 32SOIC |
| MC34712EPR2 | IC CONVERTER DDR 24QFN |
| MC34713EPR2 | IC CONVERTER DDR 24QFN |
| MC34716EPR2 | IC CONVERTER DDR 26QFN |
| MC34717EPR2 | IC CONVERTER DDR 26QFN |
相关代理商/技术参数 |
参数描述 |
|---|---|
| MC34708VMR2 | 功能描述:PMIC 解决方案 PMIC 5S 6LDO BST 10BTADC RoHS:否 制造商:Texas Instruments 安装风格:SMD/SMT 封装 / 箱体:QFN-24 封装:Reel |
| MC34709 | 制造商:SPC Multicomp 功能描述:HEADER R/ANGLE 12WAY 制造商:SPC Multicomp 功能描述:HEADER, R/ANGLE, 12WAY 制造商:SPC Multicomp 功能描述:WIRE-BOARD CONN, RECEPTACLE, 12POS, 3MM; Series:2261(5561); Pitch Spacing:3mm; Contact Termination:Through Hole Right Angle; No. of Contacts:12; No. of Rows:2; Connector Mounting:PCB; Gender:Receptacle; Contact Material:Copper Alloy ;RoHS Compliant: Yes |
| MC34709VK | 功能描述:PMIC 解决方案 PMIC 5SW, 6 LDO BST, 10 Bit ADC RoHS:否 制造商:Texas Instruments 安装风格:SMD/SMT 封装 / 箱体:QFN-24 封装:Reel |
| MC34709VKR2 | 功能描述:PMIC 解决方案 PMIC 5SW, 6 LDO BST, 10 Bit ADC RoHS:否 制造商:Texas Instruments 安装风格:SMD/SMT 封装 / 箱体:QFN-24 封装:Reel |
| MC3470N | 制造商:Texas Instruments 功能描述: |
发布紧急采购，3分钟左右您将得到回复。