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参数资料
型号： MC68302CRC16C
厂商： MOTOROLA INC
元件分类： 微控制器/微处理器
英文描述： 4 CHANNEL(S), 10M bps, LOCAL AREA NETWORK CONTROLLER, CPGA132
封装： PGA-132
文件页数： 44/128页
文件大小： 641K
代理商： MC68302CRC16C
MC68EN302 Module Bus Controller
MOTOROLA
MC68EN302 REFERENCE MANUAL
2-5
During reset, CS1, CS2 and CS3 are disabled via the EN bit in the BR1, BR2 and BR3
registers.
Note that when in disable CPU mode, the CS0 function is replaced by IOUT2.
Bits 15–8—Reserved. Should be written to zero by the host processor. These bits are
always read as zero.
CSPE—Chip Select Parity Enable. This bit enables parity checking and generation when
the corresponding Chip Select is generated. Unless the corresponding chip select is set to
8-bit operation, parity is generated and checked on both bytes.
Bits 6–5—Reserved. Should be written to zero by the host processor. This bit is always read
as zero.
FCE—Fast Cycle Enable. This bit enables fast mode operation. When using fast cycles, CS
and AS are not negated between 8 bits of a 16 bit transfer, allowing a 16-bit transfer to occur
on an 8-bit bus in 5 clocks rather than 6.
DT2–DT0—DTACK. These bits are used to determine whether DTACK is generated
internally with a programmable number of wait states or externally by the peripheral. When
done internally, the MC68EN302 provides the option of allowing 16-bit accesses to take
place in two-three clock external 8-bit accesses. The 68000 only sees a single six clock
access internally during this mode of operation. This functionality is also referred to as
‘minus one wait state option.’ Note that an 8-bit operand access requires a 4 clock bus cycle.
Table 2-4 shows how the bits are encoded.
EN8—Enable 8-bit chip select. When set to a one, the 8-bit chip select operation is enabled.
If the system is booted from an 8-bit memory, the system must drive the BUSW pin low
during system reset which sets the EN8 bit for all four CSER registers. This assures that the
device is able to access 8-bit memories as well as 16-bit memories. In 8-bit mode bits D15–
D8 of the data bus are used.
15
14
13
12
11
10
9876543210
00000000
CSPE
0
FCE
DT2
DT1
DT0
EN8
Table 2-4. DT Bit Encoding
DT BIT ENCODING
WAIT STATES
000
-1
001
0
010
1
011
2
100
3
101
4
110
5
111
No DTACK
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