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参数资料
型号： MC68302CRC16C
厂商： MOTOROLA INC
元件分类： 微控制器/微处理器
英文描述： 4 CHANNEL(S), 10M bps, LOCAL AREA NETWORK CONTROLLER, CPGA132
封装： PGA-132
文件页数： 51/128页
文件大小： 641K
代理商： MC68302CRC16C
MC68EN302 Module Bus Controller
2-12
MC68EN302 REFERENCE MANUAL
MOTOROLA
2.10.4 Parity Pin Enable
During hardware reset, the parity pin enable bit (PPE) in the MBC register (see 2.4 Module
Bus Control (MBCTL)) is cleared, which results in the parity pins becoming inputs. Each of
the three pins is sampled for a different function, as shown in Table 2-5. After exiting
hardware reset, these pins are sampled to determine chip functions. Pullup or pulldown
resistors are required for presetting the desired state if the parity pins are to be later
programmed as input/output pins. After hardware reset, the PPE bit can be set to enable the
parity pins as outputs. The PPE bit should be set to enable parity even on reads.
2.11 INTERRUPT SUPPORT
All module bus and module bus controller interrupts are at level 5 or at level 3 if MIL is set
(See 2.5 Interrupt Extension Register (IER)). There are two sources of interrupts in the MBC:
One is the Ethernet controller; the second source is the parity error interrupt. The parity error
interrupt is the higher priority of the two. If an interrupt acknowledge cycle is generated when
both interrupts are asserted, the MBC responds to the parity error interrupt by driving its
vector onto the internal 68000 bus. Only after the parity error interrupt is cleared will the
Ethernet controller respond to an IACK cycle.
In order to accommodate an additional interrupt source within the MC68EN302, an
additional Interrupt Mode (IMOD) bit is provided in the MBC. This bit configures the Interrupt
pins as IRQ or IPL lines. This replaces the MOD bit in the Global Interrupt Mode Register
(GIMR). This means that the existing MOD bit in the Global Interrupt Mode Register (GIMR)
must always remain at zero. The IMOD bit in the IER register duplicates this function in the
MBC.
Since the MBC generates a level 5 (or level 3) interrupt, and there is no way to resolve IACK
conflicts with the external circuitry, a level 5 (or level 3) interrupt should not be asserted
externally. Figure 2-8 summarizes the interrupt configuration and priorities.
Table 2-5. Parity Pin Enable Operation
PPE = 0
PIN FUNCTION
PPE = 1
PIN FUNCTION
DISCPU
PARITY0
BUSW
PARITY1
THREES
PARITYE
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