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参数资料
| 型号： | MC68302CRC16C |
| 厂商： | MOTOROLA INC |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 4 CHANNEL(S), 10M bps, LOCAL AREA NETWORK CONTROLLER, CPGA132 |
| 封装： | PGA-132 |
| 文件页数： | 84/128页 |
| 文件大小： | 641K |
| 代理商： | MC68302CRC16C |
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ETHERNET Controller
4-20
MC68EN302 REFERENCE MANUAL
MOTOROLA
The transmit FIFO control logic provides a signal indicating data is available to the Ethernet
transmit protocol machine. If underflow occurs, the Ethernet transmit protocol machine will
handle aborting the frame (append a bad CRC) and flushing the remainder of the frame from
the FIFO.
If a collision occurs within the slot time in a transmit frame, the FIFO supports retry by
maintaining a separate start of frame pointer (read lag pointer). New data is never written on
top of start of frame data until the slot time has passed. Two control signals pass between
the Ethernet transmit logic and the transmit FIFO to indicate when the slot time (collision
window) has been passed (Transmit Accept) or when a collision retry must take place
(Transmit Retry).
4.4.2 RECEIVE FIFO
The receive FIFO control logic provides “data available” and “receive FIFO empty” flow
control signals to the receive DMA controller. The “data available” signal is asserted as a
function of the number of bytes available in the FIFO and the WMRK bits from the EDMA
register. If overflow occurs, the STATUS word will have the OU bit set which will be written
into the receive BD. The frame should be discarded by software.
Data is written into the receive FIFO by the Ethernet receive logic in the case of status
information, and by the address recognition logic if the Reason and ARIndex fields are
enabled.
The receive FIFO control logic maintains a “start of frame” pointer that allows purging
collision fragments from the FIFO so that they need not be DMA’d. This purging of fragments
(runt frames less than 64 bytes long) is automatic and cannot be disabled.
4.5 ETHERNET PROTOCOL LOGIC
This block implements the MAC (media access control) sublayer of the IEEE 802.3
standard, supporting operation up to 10 Mbps compliant with both Ethernet and 802.3
standards. This logic is subdivided into transmit, receive and loopback/serial interface
sections.
4.5.1 ETHERNET TRANSMIT
The Ethernet transmiter block performs the following functions:
Parallel to serial conversion of data
Encapsulation of transmit frames
— Generation of preamble (PA) and start of frame delimiter (SFD)
— Transmits serial data from the transmit FIFO interface
— Pads short frames (with 0’s)
— Appends CRC, if required
— Appends bad CRC if required
— Appends JAM pattern (all 1’s)
Transmit Protocol
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相关代理商/技术参数 |
参数描述 |
|---|---|
| MC68302CRC20 | 制造商:MOTOROLA 制造商全称:Motorola, Inc 功能描述:Integrated Multiprotocol Processor User’s Manual |
| MC68302CRC20C | 功能描述:微处理器 - MPU 68K INTGR COM PROC DMA RoHS:否 制造商:Atmel 处理器系列:SAMA5D31 核心:ARM Cortex A5 数据总线宽度:32 bit 最大时钟频率:536 MHz 程序存储器大小:32 KB 数据 RAM 大小:128 KB 接口类型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作电源电压:1.8 V to 3.3 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-324 |
| MC68302EH16C | 功能描述:微处理器 - MPU 68K INTGR COM PROC DMA RoHS:否 制造商:Atmel 处理器系列:SAMA5D31 核心:ARM Cortex A5 数据总线宽度:32 bit 最大时钟频率:536 MHz 程序存储器大小:32 KB 数据 RAM 大小:128 KB 接口类型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作电源电压:1.8 V to 3.3 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-324 |
| MC68302EH16C | 制造商:Freescale Semiconductor 功能描述:32-Bit Microcontroller IC |
| MC68302EH16CB1 | 功能描述:微处理器 - MPU 68K INTGR COM PROC DMA RoHS:否 制造商:Atmel 处理器系列:SAMA5D31 核心:ARM Cortex A5 数据总线宽度:32 bit 最大时钟频率:536 MHz 程序存储器大小:32 KB 数据 RAM 大小:128 KB 接口类型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作电源电压:1.8 V to 3.3 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-324 |
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