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参数资料
型号： MC68302CRC16C
厂商： MOTOROLA INC
元件分类： 微控制器/微处理器
英文描述： 4 CHANNEL(S), 10M bps, LOCAL AREA NETWORK CONTROLLER, CPGA132
封装： PGA-132
文件页数： 77/128页
文件大小： 641K
代理商： MC68302CRC16C
ETHERNET Controller
MOTOROLA
MC68EN302 REFERENCE MANUAL
4-13
The BDSIZE field in the EDMA register allows the user to define up to sixty-four buffers for
the transmit channel and up to one hundred twenty buffers for the receive channel. The total
number of combined transmit and receive buffers is one-hundred-twenty-eight. Each BD
table, transmit and receive, forms a circular queue with separate transmit Buffer Descriptor
and receive Buffer Descriptor pointers maintained in the hardware. The length of the circular
queues may also be controlled by using the W (wrap) bit in the buffer descriptors.
If the transmit FIFO empties of data before the end of the frame, an underrun occurs and a
bad CRC is appended to the partially transmitted data. In addition, the UN bit is set in the
last BD of the affected frame. Transmit underrun may occur if the Ethernet controller can not
access the 68000 bus or if the next BD in the frame is not available.
During the receive process, if data from a frame is available but no BD is available, the BSY
interrupt is generated, warning the user that data will soon be lost if a BD does not become
available. If the receive FIFO overruns because there is no available BD or the Ethernet
controller can not access the 68000 bus, then the last BD for the receive frame will have the
OV bit set.
4.2.1 ETHERNET RECEIVE BUFFER DESCRIPTOR (RX BD)
The user initializes the E, W, I, and (optionally) RO bits in the first word and the pointer in
3rd and 4th words of the receive buffer descriptor. The Ethernet controller writes the
following status bits:
First word: E, L, F, M, LG, NO, SH, CR, OV and CL bits. The M, LG, NO, SH, CR, OV
and CL bits in the first word of the buffer descriptor are only modified by the Ethernet
controller when the L bit is set
Second word: the buffer length
Third word: the Reason and ARIndex fields if the INDEX_EN bit in the AR_CNTRL
register is set.
Figure 4-2. Ethernet Receive Buffer Descriptor (Rx BD)
The first word of the receive buffer descriptor contains status and control information
concerning buffer descriptor handling and data flow. These status and control bits are
described in the following paragraphs.
Offset + 0
Offset + 2
Offset + 4
Offset + 6
Rx Data Buffer Pointer - A15–A0
Data Length
CL
OV
CR
SH
NO
LG
-
M
-
F
L
I
W
RO
E
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
ARIndex
Reason
A23–A16
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