Introduction
1-4
MC68322 USER’S MANUAL
MOTOROLA
1.2.2 Graphics Unit
The graphics unit performs all graphics functions required by complex PDLs, such as
bit-block transfer (bitBLT). A bitBLT is a CPU-intensive function of logically bits from one
memory location to another. The graphics unit acts as a dedicated hardware execution
engine to perform the bitBLT function with virtually no intervention from the core. bitBLT
operations are performed very fast by the graphics unit, supporting one, two, and three
operand bitBLT operations to yield 256 logical bitBLT operation combinations.
The graphics unit contains two independent processing units that can function in parallel
with the core—a RISC graphics processor (RGP) and a print engine video controller (PVC).
Both processing units perform burst read and write accesses to DRAM through the DRAM
controller. The RGP is a high-performance bit-image processor optimized for the 16-bit
DRAM controller on the MC68322. It achieves performance levels that enable the MC68322
to be used effectively in banding applications or in other high-speed, high-density bitmapped
graphics products. The RGP is comprised of four major blocks:
Graphic order parser
Graphic order execution unit
Writeback logic
Band control registers
The PVC contains a generic nonimpact printer communication interface, which can be used
with most of the printers currently on the market. The communications interface is 8-bit
synchronous full duplex and supports almost all laser and inkjet printers. Internal interrupt
events (if enabled) indicate that a serial command has been sent or a serial status has been
received. This interface accesses a memory-mapped register called the printer
communication interface register, which contains 8-bit command and status fields. Using
these fields, the printer communication interface controls the CBSY and SBSY signals to
provide a handshake that communicates between the PVC and the print engine. In addition
to this communication interface, the PVC also provides for serialization of the bitmap image
data through the video data output at a clock rate specified by the video clock input. A digital
phase-locked loop is also provided for those printers that do not supply a video clock source.
The RGP interprets a list of special instructions called graphic orders (a display list that the
core or host application processor generates) to render a banded bitmap page image. After
a page or band image is rendered by the RGP, the PVC converts the bitmap image into a
serial datastream and transfers the rendered page image through the video port to the print
engine. Both the RGP and PVC require only a minimal amount of initialization and
intervention by the core to produce an image and transfer it to the print engine. Figure 1-2
illustrates the data flow of the graphics unit.
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Freescale Semiconductor, Inc.
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