Parallel Port Interface
9-4
MC68322 USER’S MANUAL
MOTOROLA
SEL—SELECT Control Bit
Setting this bit drives a high level and clearing it drives a low level on SELECT.
FLT—FAULT Control Bit
Setting this bit drives a high level and clearing it drives a low level on FAULT.
9.1.2 Parallel Port Control Register
The parallel port control register (PPCR) is a read/write register containing nine bits that
configure the operation of the PPI. Figure 9-3 illustrates the PPCR.
Figure 9-3. Parallel Port Control Register
FLL—Full
This bit is a read-only status bit that indicates when parallel port data from the host is latched
in the DATA field of the PPIR. FLL is cleared when the PPIR’s DATA field is read. When
handshaking and DMA are enabled, FLL is set and then cleared as data is latched and read
during forward data transfers. The FLL bit is also cleared when the RST bit is set.
RLD—Run-Length Decompression
This bit is a read-only status bit that indicates when run-length decompression is taking
place during ECP forward data transfers. RLD is set when a run-length count is received and
loaded into the internal counter and cleared when the last of the decompressed data is read
from the PPIR’s DATA field. This bit can only be set when ECP with RLE (MODE = 11
2) is
enabled. If the MODE field is reprogrammed during decompression, decompression
continues and RLD remains set until the operation is complete. RLD is also cleared when
RST is issued.
ABT—Abort
This bit causes the PPI to use SELECTIN to detect when the host suddenly aborts a reverse
transfer and returns to compatibility mode. If ABT is set, a low level on SELECTIN causes
the PDE bit to be cleared and the PD7–PD0 output drivers to be three-stated. In fact, if ABT
is set and SELECTIN is low, setting the PDE bit has no effect. This protection logic, as with
all internal PPI logic, operates on a synchronized and optionally digitally filtered SELECTIN
that is latched into the PPIR.
Note: The FLT, SEL, PER, and BSY2 bits are arranged to correspond to their use as
parallel port data lines during nibble mode reverse data transfers. When
hardware handshaking is enabled, BUSY and ACK are controlled by the PPI
state machine. When hardware handshaking is disabled and the PPI state
machine is idle, BUSY and ACK can be controlled by the software using the
BSY2 and ACK2 bits.
FLL RLD ABT PDE ERC
MODE
DFE
00FFF300
RST
RESERVED
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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