Bus Operation
4-4
MC68322 USER’S MANUAL
MOTOROLA
4.2 EC000 CORE WRITE CYCLE
During a write cycle, the core sends data to memory (DRAM or EPROM), an internal
register, or a peripheral device; writing bytes of data in all cases. If the instruction specifies
a word (or long-word) operation, the core writes both upper and lower bytes simultaneously.
When the instruction specifies a byte operation, the core uses the internal A0 to determine
which byte to write and then issues the data strobe required for that byte.
A transfer is initiated by asserting the address strobe (AS) and providing a valid internal
function code and address. The address is decoded by each module. Once a transfer is
initiated, the core uses the timing and wait state characteristics for the active interface to
pace the internal core bus cycle. Using the wait state information of the selected module,
the core waits the specified number of cycles, transfers data, and then terminates the cycle
by asserting the internal DTACK signal to the core. The core, in turn, then terminates the
internal core bus cycle within two clocks (S4–S7). All transfers on the internal core bus
require the minimum access time of four clock cycles. Figure 4-5 illustrates the write cycle
flowchart and Figure 4-6 illustrates the word and byte write cycle timing diagram to
chip-selects.
Figure 4-5. Write Cycle Flowchart
EC000 CORE
ADDRESS THE DEVICE
ACQUIRE THE DATA
TERMINATE THE CYCLE
INPUT THE DATA
BUS INTERFACE UNIT
1) DECODE ADDRESS
2) ASSERT CHIP-SELECT (MC68322
BUS ONLY)
3) ASSERT WRU AND WRL DEPENDING
ON UDS AND LDS (MC68322 BUS
ONLY)
4) ASSERT MULTIPLEXED ADDRESS
ON MA10–MA0 (DRAM ONLY)
5) ASSERT CS1 AND CS0 DEPENDING
ON UDS AND LDS (DRAM ONLY)
6) ASSERT RAS (DRAM ONLY)
7) WRITE DATA FROM DESTINATION
8) RECEIVE DATA ON INTERNAL
D15–D0
9) ASSERT INTERNAL DTACK
10) ASSERT WAIT TO STALL EXTERNAL
MC68322 BUS ACCESS (OPTIONAL)
1) PLACE ADDRESS ON A27–A0
2) ASSERT AS (MC68322 BUS ONLY)
4) ASSERT R/W
1) REMOVE DATA FROM INTERNAL
D15–D0
2) NEGATE AS
3) SET R/W TO READ
2) NEGATE INTERNAL DTACK
2) NEGATE WRU AND WRL (MC68322
BUS ONLY)
3) NEGATE MA10–MA0, WE, RAS, AND
CAS (DRAM ONLY)
START NEXT CYCLE
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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