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参数资料
型号： MC68HCP11A1CFNE3
厂商： MOTOROLA INC
元件分类： 微控制器/微处理器
英文描述： 8-BIT, EEPROM, 3 MHz, MICROCONTROLLER, PQCC52
封装： PLASTIC, LCC-52
文件页数： 10/158页
文件大小： 776K
代理商： MC68HCP11A1CFNE3
MC68HC11A8
CPU, ADDRESSING MODES, AND INSTRUCTION SET
MOTOROLA
TECHNICAL DATA
10-9
10
LDS (opr)
Load Stack Pointer
M:M + 1
→ SP
IMM
DIR
EXT
IND,X
IND,Y
8E
9E
BE
AE
18 AE
jj
kk
dd
hh
ll
ff
3
2
3
2
3
4
5
6
3-2
4-3
5-4
6-6
7-6
- - - - ¤ ¤ 0 -
LDX (opr)
Load Index Register X
M:M + 1
→ IX
IMM
DIR
EXT
IND,X
IND,Y
CE
DE
FE
EE
CD EE
jj
kk
dd
hh
ll
ff
3
2
3
2
3
4
5
6
3-2
4-3
5-4
6-6
7-6
- - - - ¤ ¤ 0 -
LDY (opr)
Load Index Register Y
M:M + 1
→ IY
IMM
DIR
EXT
IND,X
IND,Y
18 CE
18 DE
18 FE
1A EE
18 EE
jj
kk
dd
hh
ll
ff
4
3
4
3
4
5
6
3-4
4-5
5-6
6-7
7-6
- - - - ¤ ¤ 0 -
LSL (opr)
Logical Shift Left
EXT
IND,X
IND,Y
A INH
B INH
78
68
18 68
48
58
hh
ll
ff
3
2
3
1
6
7
2
5-8
6-3
3-7
2-1
- - - - ¤ ¤ ¤ ¤
LSLA
LSLB
LSLD
Logical Shift Left Double
INH
05
1
3
2-2
- - - - ¤ ¤ ¤ ¤
LSR (opr)
Logical Shift Right
EXT
IND,X
IND,Y
A INH
B INH
74
64
18 64
44
54
hh
ll
ff
3
2
3
1
6
7
2
5-8
6-3
7-3
2-1
- - - - ¤ ¤ ¤ ¤
LSRA
LSRB
LSRD
Logical Shift Right Double
INH
04
1
3
2-2
- - - - 0 ¤ ¤ ¤
MUL
Multiply 8 by 8
AxB
→ D
INH
3D
1
10
2-13
- - - - - - - ¤
NEG (opr)
2’s Complement Memory Byte 0 – M
→ M
EXT
IND,X
IND,Y
70
60
18 60
hh ll
ff
3
2
3
6
7
5-8
6-3
7-3
- - - - ¤ ¤ ¤ ¤
NEGA
2’s Complement A
0 – A
→ A
A INH
40
1
2
2-1
- - - - ¤ ¤ ¤ ¤
NEGB
2’s Complement B
0 – B
→ B
B INH
50
1
2
2-1
- - - - ¤ ¤ ¤ ¤
NOP
No Operation
INH
01
1
2
2-1
- - - - - - - -
ORAA (opr) OR Accumulator A (Inclusive) A + M
→ A
A IMM
A DIR
A EXT
A IND,X
A IND,Y
8A
9A
BA
AA
18 AA
ii
dd
hh
ll
ff
2
3
2
3
2
3
4
5
3-1
4-1
5-2
6-2
7-2
- - - - ¤ ¤ 0 -
ORAB (opr) OR Accumulator B (Inclusive) B + M
→ B
B IMM
B DIR
B EXT
B IND,X
B IND,Y
CA
DA
FA
EA
18 EA
ii
dd
hh
ll
ff
2
3
2
3
2
3
4
5
3-1
4-1
5-2
6-2
7-2
- - - - ¤ ¤ 0 -
PSHA
Push A onto Stack
A
→ Stk, SP = SP–1
A INH
36
1
3
2-6
- - - - - - - -
PSHB
Push B onto Stack
B
→ Stk, SP = SP–1
B INH
37
1
3
2-6
- - - - - - - -
PSHX
Push X onto Stack (Lo First)
IX
→ Stk, SP = SP–2
INH
3C
1
4
2-7
- - - - - - - -
PSHY
Push Y onto Stack (Lo First)
IY
→ Stk, SP = SP–2
INH
18 3C
2
5
2-8
- - - - - - - -
PULA
Pull A from Stack
SP = SP + 1, A
←Stk
A INH
32
1
4
2-9
- - - - - - - -
PULB
Pull B from Stack
SP = SP + 1, B
←Stk
B INH
33
1
4
2-9
- - - - - - - -
PULX
Pull X from Stack (Hi First)
SP = SP + 2, IX
←Stk
INH
38
1
5
2-10
- - - - - - - -
PULY
Pull Y from Stack (Hi First)
SP = SP + 2, IY
←Stk
INH
18 38
2
6
2-11
- - - - - - - -
ROL (opr)
Rotate Left
EXT
IND,X
IND,Y
A INH
B INH
79
69
18 69
49
59
hh
ll
ff
3
2
3
1
6
7
2
5-8
6-3
7-3
2-1
- - - - ¤ ¤ ¤ ¤
ROLA
ROLB
Table 10-1 MC68HC11A8 Instructions, Addressing Modes, and Execution Times
(Sheet 4 of 6)
Source
Form(s)
Operation
Boolean Expression
Addressing
Mode for
Operand
Machine Coding
(Hexadecimal)
Bytes
Cycle
by
Cycle*
Condition Codes
Opcode
Operand(s)
S X H I N Z V C
*Cycle-by-cycle number provides a reference to Tables 10-2 through 10-8 which detail cycle-by-cycle operation.
Example: Table 10-1 Cycle-by-Cycle column reference number 2-4 equals Table 10-2 line item 2-4.
Cb0
b7
0
Cb0
b15
0
C
b0
b7
0
C
b0
b15
0
C
b0
b7
C
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