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参数资料
型号： MC68HCP11A1CFNE3
厂商： MOTOROLA INC
元件分类： 微控制器/微处理器
英文描述： 8-BIT, EEPROM, 3 MHz, MICROCONTROLLER, PQCC52
封装： PLASTIC, LCC-52
文件页数： 146/158页
文件大小： 776K
代理商： MC68HCP11A1CFNE3
MOTOROLA
RESETS, INTERRUPTS, AND LOW POWER MODES
MC68HC11A8
9-8
TECHNICAL DATA
9
into two basic categories, maskable and non-maskable. In the MC68HC11A8 fifteen
of the interrupts can be masked using the condition code register I bit. In addition to
being maskable by the I bit in the condition code register, all of the on-chip interrupt
sources are individually maskable by local control bits.
The software interrupt (SWI instruction) is a non-maskable instruction rather than a
maskable interrupt source. The illegal opcode interrupt is a non-maskable interrupt.
The last interrupt source, external input to the XIRQ pin, is considered a non-maskable
interrupt because once enabled, it cannot be masked by software; however, it is
masked during reset and upon receipt of an interrupt at the XIRQ pin. Table 9-2, Table
9-3, and Table 9-4 provide a list of each interrupt, its vector location in memory, and
the actual condition code and control bits that mask it. A discussion of the various in-
terrupts is provided below. Figure 9-3 shows the interrupt stacking order.
Table 9-2 IRQ Vector Interrupts
Interrupt Cause
Local Mask
External Pin
None
Parallel l/O Handshake
STAI
Table 9-3 Interrupt Vector Assignments
Vector
Interrupt Source
CC
Local Mask
Address
Register Mask
FFC0, C1
Reserved
—
FFD4, D5
Reserved
—
FFD6, D7
SCI Serial System
I Bit
See Table 9-3
FFD8, D9
SPI Serial Transfer Complete
I Bit
SPIE
FFDA, DB
Pulse Accumulator Input Edge
I Bit
PAII
FFDC, DD
Pulse Accumulator Overflow
I Bit
PAOVI
FFDE, DF
Timer Overflow
I Bit
TOI
FFE0, E1
Timer Output Compare 5
I Bit
OC5I
FFE2, E3
Timer Output Compare 4
I Bit
OC4I
FFE4, E5
Timer Output Compare 3
I Bit
OC3I
FFE6, E7
Timer Output Compare 2
I Bit
OC2I
FFE8, E9
Timer Output Compare 1
I Bit
OC1I
FFEA, EB
Timer Input Capture 3
I Bit
OC3I
FFEC, ED
Timer Input Capture 2
I Bit
OC2I
FFEE, EF
Timer Input Capture 1
I Bit
OC1I
FFF0, F1
Real Time Interrupt
I Bit
RTII
FFF2, F3
IRQ (External Pin or Parallel l/O)
I Bit
See Table 9-4
FFF4, F5
XIRQ Pin (Pseudo Non-Maskable Interrupt)
X Bit
None
FFF6, F7
SWI
None
FFF8, F9
Illegal Opcode Trap
None
FFFA, FB
COP Failure (Reset)
None
NOCOP
FFFC, FD
COP Clock Monitor Fail (Reset)
None
CME
FFFE, FF
RESET
None
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