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参数资料
型号： MC68HCP11A1CFNE3
厂商： MOTOROLA INC
元件分类： 微控制器/微处理器
英文描述： 8-BIT, EEPROM, 3 MHz, MICROCONTROLLER, PQCC52
封装： PLASTIC, LCC-52
文件页数： 47/158页
文件大小： 776K
代理商： MC68HCP11A1CFNE3
MOTOROLA
ELECTRICAL CHARACTERISTICS
MC68HC11A8
A-20
TECHNICAL DATA
A
NOTES:
1. Formula only for dc to 2 MHz.
2. Input clocks with duty cycles other than 50% affect bus performance. Timing parameters affected by input clock
duty cycle are identified by (a) and (b). To recalculate the approximate bus timing values, substitute the following
expressions in place of 1/8 tcyc in the above formulas, where applicable:
(a) (1-DC) x 1/4 tcyc
(b) DC x 1/4 tcyc
Where:
DC is the decimal value of duty cycle percentage (high time).
3. All timing is shown with respect to 20% VDD and 70% VDD, unless otherwise noted.
Table A-7a Expansion Bus Timing (MC68L11A8)
VDD = 3.0 Vdc to 5.5 Vdc, VSS = 0 Vdc, TA = TL to TH
Num
Characteristic
Symbol
1.0 MHz
2.0 MHz
Unit
Min
Max
Min
Max
Frequency of Operation (E-Clock Frequency)
fo
dc
1.0
dc
2.0
MHz
1
Cycle Time
tcyc
1000
—
500
—
ns
2
Pulse Width, E Low
PWEL = 1/2 tcyc – 23 ns
(Note 1)
PWEL
475
—
225
—
ns
3
Pulse Width, E High
PWEH = 1/2 tcyc – 28 ns
(Note 1)
PWEH
470
—
220
—
ns
4a, b E and AS Rise and Fall Time
tr
tf
—25
25
—25
25
ns
9
Address Hold Time
tAH = 1/8 tcyc – 29.5 ns
(Note 1, 2a)
tAH
95—33—
ns
12
Non-Muxed Address Valid Time to E Rise
tAV = PWEL – (tASD + 80 ns)
(Note 1, 2a)
tAV
275
—
88
—
ns
17
Read Data Setup Time
tDSR
30—30—
ns
18
Read Data Hold Time (Max = tMAD)tDHR
0
150
0
88
ns
19
Write Data Delay Time
tDDW = 1/8 tcyc + 65.5 ns
(Note 1, 2a)
tDDW
—
195
—
133
ns
21
Write Data Hold Time
tDHW = 1/8 tcyc – 29.5 ns
(Note 1, 2a)
tDHW
95—33—
ns
22
Muxed Address Valid Time to E Rise
tAVM = PWEL – (tASD + 90 ns)
(Note 1, 2a)
tAVM
265
—
78
—
ns
24
Muxed Address Valid Time to AS Fall
tASL = PWASH – 70 ns
(Note 1)
tASL
150
—
25
—
ns
25
Muxed Address Hold Time
tAHL = 1/8 tcyc – 29.5 ns
(Note 1, 2b)
tAHL
95—33—
ns
26
Delay Time, E to AS Rise
tASD = 1/8 tcyc – 9.5 ns
(Note 1, 2a)
tASD
120
—
58
—
ns
27
Pulse Width, AS High
PWASH = 1/4 tcyc – 29 ns
(Note 1)
PWASH
220
—
95
—
ns
28
Delay Time, AS to E Rise
tASED = 1/8 tcyc – 9.5 ns
(Note 1, 2b)
tASED
120
—
58
—
ns
29
MPU Address Access Time
(Note 2a)
tACCA = tcyc – (PWEL – tAVM) – tDSR – tf
tACCA
735
—
298
—
ns
35
MPU Access Time
tACCE = PWEH – tDSR
tACCE
—
440
—
190
ns
36
Muxed Address Delay
(Previous Cycle MPU Read)
tMAD = tASD + 30 ns
(Note 1, 2a)
tMAD
150
—
88
—
ns
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