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参数资料
型号： MC68HCP11A1CFNE3
厂商： MOTOROLA INC
元件分类： 微控制器/微处理器
英文描述： 8-BIT, EEPROM, 3 MHz, MICROCONTROLLER, PQCC52
封装： PLASTIC, LCC-52
文件页数： 19/158页
文件大小： 776K
代理商： MC68HCP11A1CFNE3
MC68HC11A8
CPU, ADDRESSING MODES, AND INSTRUCTION SET
MOTOROLA
TECHNICAL DATA
10-17
10
4-3
LDD, LDS, LDX
4
1
2
3
4
Opcode Address
Opcode Address + 1
Operand Address
Operand Address + 1
1
Opcode
Operand Address (Low Byte)
(High Byte Assumed to be $00)
Operand Data (High Byte)
Operand Data (Low Byte)
4-4
STD, STS, STX
4
1
2
3
4
Opcode Address
Opcode Address + 1
Operand Address
Operand Address + 1
1
0
Opcode
Operand Address (Low Byte)
(High Byte Assumed to be $00)
Register Data (High Byte)
Register Data (Low Byte)
4-5
LDY
5
1
2
3
4
5
Opcode Address
Opcode Address + 1
Opcode Address + 2
Operand Address
Operand Address + 1
1
Opcode (Page Select Byte)
($18)
Opcode (Second Byte) ($DE)
Operand Address (Low Byte)
(High Byte Assumed to be $00)
Operand Data (High Byte)
Operand Data (Low Byte)
4-6
STY
5
1
2
3
4
5
Opcode Address
Opcode Address + 1
Opcode Address + 2
Operand Address
Operand Address + 1
1
0
Opcode (Page Select Byte)
($18)
Opcode (Second Byte) ($DF)
Operand Address (Low Byte)
(High Byte Assumed to be $00)
Register Data (High Byte)
Register Data (Low Byte)
4-7
ADDD, CPX, SUBD
5
1
2
3
4
5
Opcode Address
Opcode Address + 1
Operand Address
Operand Address + 1
$FFFF
1
Opcode
Operand Address (Low Byte)
(High Byte Assumed to be $00)
Operand Data (High Byte)
Operand Data (Low Byte)
Irrelevant Data
4-8
JSR
5
1
2
3
4
5
Opcode Address
Opcode Address + 1
Subroutine Address
Stack Pointer
Stack Pointer – 1
1
0
Opcode ($9D)
Subroutine Address (Low Byte)
(High Byte Assumed to be $00)
First Subroutine Opcode
Return Address (Low Byte)
Return Address (High Byte)
4-9
CPD, CPY
6
1
2
3
4
5
6
Opcode Address
Opcode Address + 1
Opcode Address + 2
Operand Address
Operand Address + 1
$FFFF
1
Opcode (Page Select Byte)
Opcode (Second Byte)
Operand Address (Low Byte)
(High Byte Assumed to be $00)
Operand Data (High Byte)
Operand Data (Low Byte)
Irrelevant Data
4-10
BCLR, BSET
6
1
2
3
4
5
6
Opcode Address
Opcode Address + 1
Operand Address
Opcode Address + 2
$FFFF
Operand Address
1
0
Opcode
Operand Address (Low Byte)
(High Byte Assumed to be $00)
Original Operand Data
Mask Byte
Irrelevant Data
Result Operand Data
4-11
BRCLR, BRSET
6
1
2
3
4
5
6
Opcode Address
Opcode Address + 1
Operand Address
Opcode Address + 2
Opcode Address + 3
$FFFF
1
Opcode
Operand Address (Low Byte)
(High Byte Assumed to be $00)
Original Operand Data
Mask Byte
Branch Offset
Irrelevant Data
Table 10-4 Cycle-by-Cycle Operation — Direct Mode (Sheet 2 of 2)
Reference
Number*
Address Mode
and Instructions
Cycles Cycle
#
Address Bus
R/W
Line
Data Bus
*The reference number is given to provide a cross-refrerence to Table 10-1.
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