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参数资料
型号： MC68HCP11A1CFNE3
厂商： MOTOROLA INC
元件分类： 微控制器/微处理器
英文描述： 8-BIT, EEPROM, 3 MHz, MICROCONTROLLER, PQCC52
封装： PLASTIC, LCC-52
文件页数： 109/158页
文件大小： 776K
代理商： MC68HCP11A1CFNE3
MOTOROLA
SERIAL COMMUNICATIONS INTERFACE
MC68HC11A8
5-10
TECHNICAL DATA
5
5.8.4 Serial Communications Status Register (SCSR)
The serial communications status register (SCSR) provides inputs to the interrupt logic
circuits for generation of the SCI system interrupt.
TDRE — Transmit Data Register Empty
The transmit data register empty bit is set to indicate that the content of the serial com-
munications data register have been transferred to the transmit serial shift register.
This bit is cleared by reading the SCSR (with TDRE = 1) followed by a write to the
SCDR.
TC — Transmit Complete
The transmit complete bit is set at the end of a data frame, preamble, or break condi-
tion if:
1. TE = 1, TDRE = 1, and no pending data, preamble, or break is to be transmitted;
or
2. TE = 0, and the data, preamble, or break in the transmit shift register has been
transmitted.
The TC bit is a status flag which indicates that one of the above conditions have oc-
curred.
The TC bit is cleared by reading the SCSR (with TC set) followed by a write to the
SCDR.
RDRF — Receive Data Register Full
The receive data register full bit is set when the receiver serial shift register is transferred to
the SCDR. The RDRF bit is cleared when the SCSR is read (with RDRF set) followed by a
read of the SCDR.
IDLE — Idle Line Detect
The idle line detect bit, when set, indicates the receiver has detected an idle line. The IDLE
bitisclearedbyreadingtheSCSRwithIDLEsetfollowedbyreadingSCDR.OncetheIDLE
status flag is cleared, it will not be set again until after the RxD line has been active and be-
comes idle again.
OR — Overrun Error
Theoverrunerrorbitissetwhenthenextbyteisreadytobetransferredfromthereceiveshift
register to the SCDR which is already full (RDRF bit is set). When an overrun error occurs,
thedatawhichcausedtheoverrunislostandthedatawhichwasalreadyinSCDRisnotdis-
turbed. The OR is cleared when the SCSR is read (with OR set), followed by a read of the
SCDR.
7
654321
0
$102E
TDRE
TC
RDRF
IDLE
OR
NF
FE
0
SCSR
RESET
11000000
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