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参数资料
型号： MC68HCP11A1CFNE3
厂商： MOTOROLA INC
元件分类： 微控制器/微处理器
英文描述： 8-BIT, EEPROM, 3 MHz, MICROCONTROLLER, PQCC52
封装： PLASTIC, LCC-52
文件页数： 8/158页
文件大小： 776K
代理商： MC68HCP11A1CFNE3
MC68HC11A8
CPU, ADDRESSING MODES, AND INSTRUCTION SET
MOTOROLA
TECHNICAL DATA
10-7
10
BITA (opr)
Bit(s) Test A with Memory
AM
A IMM
A DIR
A EXT
A IND,X
A IND,Y
85
95
B5
A5
18 A5
ii
dd
hh
ll
ff
2
3
2
3
2
3
4
5
3-1
4-1
5-2
6-2
7-2
- - - - ¤ ¤ 0 -
BITB (opr)
Bit(s) Test B with Memory
BM
B IMM
B DIR
B EXT
B IND,X
B IND,Y
C5
D5
F5
E5
18 E5
ii
dd
hh
ll
ff
2
3
2
3
2
3
4
5
3-1
4-1
5-2
6-2
7-2
- - - - ¤ ¤ 0 -
BLE (rel)
Branch if
≤ Zero
? Z + (N
⊕ V) = 1
REL
2F rr
2
3
8-1
- - - - - - - -
BLO (rel)
Branch if Lower
? C = 1
REL
25 rr
2
3
8-1
- - - - - - - -
BLS (rel)
Branch if Lower or Same
? C + Z = 1
REL
23 rr
2
3
8-1
- - - - - - - -
BLT (rel)
Branch If < Zero
? N
⊕ V = 1
REL
2D rr
2
3
8-1
- - - - - - - -
BMI (rel)
Branch if Minus
? N = 1
REL
2B rr
2
3
8-1
- - - - - - - -
BNE (rel)
Branch if Not = Zero
? Z = 0
REL
26 rr
2
3
8-1
- - - - - - - -
BPL (rel)
Branch if Plus
? N = 0
REL
2A rr
2
3
8-1
- - - - - - - -
BRA (rel)
Branch Always
? 1 = 1
REL
20 rr
2
3
8-1
- - - - - - - -
BRCLR(opr)
(msk)
(rel)
Branch if Bit(s) Clear
? M mm = 0
DIR
IND,X
IND,Y
13
1F
18 1F
dd mm rr
ff mm rr
4
5
6
7
8
4-11
6-14
7-11
- - - - - - - -
BRN (rel)
Branch Never
? 1 = 0
REL
21 rr
2
3
8-1
- - - - - - - -
BRSET(opr)
(msk)
(rel)
Branch if Bit(s) Set
? (M) mm = 0
DIR
IND,X
IND,Y
12
1E
18 1E
dd mm rr
ff mm rr
4
5
6
7
8
4-11
6-14 7-
11
- - - - - - - -
BSET(opr)
(msk)
Set Bit(s)
M + mm
→ M
DIR
IND,X
IND,Y
14
1C
18 1C
dd mm
ff mm
3
4
6
7
8
4-10
6-13
7-10
- - - - ¤ ¤ 0 -
BSR (rel)
Branch to Subroutine
See Special Ops
REL
8D rr
2
6
8-2
- - - - - - - -
BVC (rel)
Branch if Overflow Clear
? V = 0
REL
28 rr
2
3
8-1
- - - - - - - -
BVS (rel)
Branch if Overflow Set
? V = 1
REL
29 rr
2
3
8-1
- - - - - - - -
CBA
Compare A to B
A – B
INH
11
1
2
2-1
- - - - ¤ ¤ ¤ ¤
CLC
Clear Carry Bit
0
→ C
INH
0C
1
2
2-1
- - - - - - - 0
CLI
Clear Interrupt Mask
0
→ l
INH
0E
1
2
2-1
- - - 0 - - - -
CLR (opr)
Clear Memory Byte
0
→ M
EXT
IND,X
IND,Y
7F
6F
18 6F
hh
ll
ff
3
2
3
6
7
5-8
6-3
7-3
- - - - 0 1 0 0
CLRA
Clear Accumulator A
0
→ A
A INH
4F
1
2
2-1
- - - - 0 1 0 0
CLRB
Clear Accumulator B
0
→ B
B INH
5F
1
2
2-1
- - - - 0 1 0 0
CLV
CIear Overflow Flag
0
→ V
INH
0A
1
2
2-1
- - - - - - 0 -
CMPA (opr) Compare A to Memory
A – M
A IMM
A DIR
A EXT
A IND,X
A IND,Y
81
91
B1
A1
18 A1
ii
dd
hh
ll
ff
2
3
2
3
2
3
4
5
3-1
4-1
5-2
6-2
7-2
- - - - ¤ ¤ ¤ ¤
CMPB (opr) Compare B to Memory
B – M
B IMM
B DIR
B EXT
B IND,X
B IND,Y
C1
D1
F1
E1
18 E1
ii
dd
hh
ll
ff
2
3
2
3
2
3
4
5
3-1
4-1
5-2
6-2
7-2
- - - - ¤ ¤ ¤ ¤
COM (opr)
1’s Complement Memory Byte $FF – M
→ M
EXT
IND,X
IND,Y
73
63
18 63
hh
ll
ff
3
2
3
6
7
5-8
6-3
7-3
- - - - ¤ ¤ 0 1
COMA
1’s Complement A
$FF – A
→ A
A INH
43
1
2
2-1
- - - - ¤ ¤ 0 1
COMB
1’s Complement B
$FF – B
→ B
B INH
53
1
2
2-1
- - - - ¤ ¤ 0 1
CPD (opr)
Compare D to Memory 16-Bit
D – M:M + 1
IMM
DIR
EXT
IND,X
IND,Y
1A 83
1A 93
1A B3
1A A3
CD A3
jj
kk
dd
hh
ll
ff
4
3
4
3
5
6
7
3-5
4-9
5-11
6-11
7-8
- - - - ¤ ¤ ¤ ¤
Table 10-1 MC68HC11A8 Instructions, Addressing Modes, and Execution Times
(Sheet 2 of 6)
Source
Form(s)
Operation
Boolean Expression
Addressing
Mode for
Operand
Machine Coding
(Hexadecimal)
Bytes
Cycle
by
Cycle*
Condition Codes
Opcode
Operand(s)
S X H I N Z V C
*Cycle-by-cycle number provides a reference to Tables 10-2 through 10-8 which detail cycle-by-cycle operation.
Example: Table 10-1 Cycle-by-Cycle column reference number 2-4 equals Table 10-2 line item 2-4.
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