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参数资料
型号： MC8640DHX1250HE
厂商： FREESCALE SEMICONDUCTOR INC
元件分类： 微控制器/微处理器
英文描述： 32-BIT, 1250 MHz, MICROPROCESSOR, CBGA1023
封装： 33 X 33 MM, CERAMIC, FCBGA-1023
文件页数： 24/130页
文件大小： 1495K
代理商： MC8640DHX1250HE
MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 3
12
Freescale Semiconductor
Electrical Characteristics
Figure 3 illustrates the power up sequence as described above.
Figure 3. MPC8640 Power-Up and Reset Sequence
VDD_PLAT, AVDD_PLAT
L/T/OVDD
Time
2.5 V
3.3 V
1.2 V
0
DC
P
o
wer
Su
ppl
y
V
o
lt
age
Reset
Configuration Pins
HRESET (& TRST)
100 s Platform PLL
Asserted for
100
μs after
Power Supply Ramp Up 2
Notes:
1. Dotted waveforms correspond to optional supply values for a specified power supply. See Table 2.
2. The recommended maximum ramp up time for power supplies is 20 milliseconds.
3. Refer to Section 5, “RESET Initialization,” for additional information on PLL relock and reset signal
assertion timing requirements.
4. Refer to Table 11 for additional information on reset configuration pin setup timing requirements. In
addition see Figure 68 regarding HRESET and JTAG connection details including TRST.
5. e600 PLL relock time is 100 microseconds maximum plus 255 MPX_clk cycles.
6. Stable PLL configuration signals are required as stable SYSCLK is applied. All other POR configuration
inputs are required 4 SYSCLK cycles before HRESET negation and are valid at least 2 SYSCLK cycles
after HRESET has negated (hold requirement). See Section 5, “RESET Initialization,” for more
information on setup and hold time of reset configuration signals.
7. VDD_PLAT, AVDD_PLAT must strictly reach 90% of their recommended voltage before the rail for
D
n_GVDD, and Dn_MVREF reaches 10% of their recommended voltage.
8. SYSCLK must be driven only AFTER the power for the various power supplies is stable.
9. In device sleep mode, the reset configuration signals for DRAM types (TSEC2_TXD[4],TSEC2_TX_ER)
must be valid BEFORE HRESET is asserted.
e6005
AVDD_LB, SVDD, XVDD_SRDSn
VDD_Coren, AVDD_Coren
AVDD_SRDSn
1.8 V
D
n_GVDD, = 1.8/2.5 V
D
n_MVREF
If
SYSCLK 8 (not drawn to scale)
Relock Time 3
L/TVDD=2.5 V
1
7
PLL
9
SYSCLK is functional 4
Cycles Setup and hold Time 6
相关PDF资料
PDF描述
MC8640DHX1067NC 32-BIT, 1067 MHz, MICROPROCESSOR, CBGA1023
MC8640DTVU1000HE 32-BIT, 1000 MHz, MICROPROCESSOR, CBGA1023
MC8640DTHX1067NC 32-BIT, 1067 MHz, MICROPROCESSOR, CBGA1023
MC8640THX1250HC 32-BIT, 1250 MHz, MICROPROCESSOR, CBGA1023
MC8640DTVU1250HE 32-BIT, 1250 MHz, MICROPROCESSOR, CBGA1023
相关代理商/技术参数
参数描述
MC8640DHX1250N 制造商:FREESCALE 制造商全称:Freescale Semiconductor, Inc 功能描述:Integrated Host Processor Hardware Specifications Addendum for the MC8640xTxxyyyyaC Series
MC8640DTHX1000H 制造商:FREESCALE 制造商全称:Freescale Semiconductor, Inc 功能描述:Integrated Host Processor Hardware Specifications
MC8640DTHX1000HC 功能描述:微处理器 - MPU G8 REV2.1 1.05V -40/105C RoHS:否 制造商:Atmel 处理器系列:SAMA5D31 核心:ARM Cortex A5 数据总线宽度:32 bit 最大时钟频率:536 MHz 程序存储器大小:32 KB 数据 RAM 大小:128 KB 接口类型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作电源电压:1.8 V to 3.3 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-324
MC8640DTHX1000HE 功能描述:微处理器 - MPU G8 REV 3.0 1.05V -40/105C RoHS:否 制造商:Atmel 处理器系列:SAMA5D31 核心:ARM Cortex A5 数据总线宽度:32 bit 最大时钟频率:536 MHz 程序存储器大小:32 KB 数据 RAM 大小:128 KB 接口类型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作电源电压:1.8 V to 3.3 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-324
MC8640DTHX1000N 制造商:FREESCALE 制造商全称:Freescale Semiconductor, Inc 功能描述:Integrated Host Processor Hardware Specifications Addendum for the MC8640xTxxyyyyaC Series
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