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参数资料
型号： MC8640DHX1250HE
厂商： FREESCALE SEMICONDUCTOR INC
元件分类： 微控制器/微处理器
英文描述： 32-BIT, 1250 MHz, MICROPROCESSOR, CBGA1023
封装： 33 X 33 MM, CERAMIC, FCBGA-1023
文件页数： 57/130页
文件大小： 1495K
代理商： MC8640DHX1250HE
MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 3
32
Freescale Semiconductor
Ethernet: Enhanced Three-Speed Ethernet (eTSEC), MII Management
8.2.3.1
MII Transmit AC Timing Specifications
Table 30 provides the MII transmit AC timing specifications.
Figure 13 shows the MII transmit AC timing diagram.
Figure 13. MII Transmit AC Timing Diagram
8.2.3.2
MII Receive AC Timing Specifications
Table 31 provides the MII receive AC timing specifications.
Table 30. MII Transmit AC Timing Specifications
At recommended operating conditions with L/TVDD of 3.3 V ± 5%.
Parameter
Symbol 1
Min
Typ
Max
Unit
TX_CLK clock period 10 Mbps
tMTX
2
—
400
—
ns
TX_CLK clock period 100 Mbps
tMTX
—40
—
ns
TX_CLK duty cycle
tMTXH/tMTX
35
—
65
%
TX_CLK to MII data TXD[3:0], TX_ER, TX_EN delay
tMTKHDX
1
5
15
ns
TX_CLK data clock rise time (20%–80%)
tMTXR
2
1.0
—
4.0
ns
TX_CLK data clock fall time (80%–20%)
tMTXF
2
1.0
—
4.0
ns
Note:
1. The symbols used for timing specifications herein follow the pattern of t(first two letters of functional block)(signal)(state) (reference)(state)
for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tMTKHDX symbolizes MII
transmit timing (MT) for the time tMTX clock reference (K) going high (H) until data outputs (D) are invalid (X). Note that, in
general, the clock reference symbol representation is based on two to three letters representing the clock of a particular
functional. For example, the subscript of tMTX represents the MII(M) transmit (TX) clock. For rise and fall times, the latter
convention is used with the appropriate letter: R (rise) or F (fall).
2. Guaranteed by design.
Table 31. MII Receive AC Timing Specifications
At recommended operating conditions with L/TVDD of 3.3 V ± 5%.
Parameter
Symbol 1
Min
Typ
Max
Unit
RX_CLK clock period 10 Mbps
tMRX
2,3
—400
—
ns
RX_CLK clock period 100 Mbps
tMRX
3
—40
—
ns
RX_CLK duty cycle
tMRXH/tMRX
35
—
65
%
TX_CLK
TXD[3:0]
tMTKHDX
tMTX
tMTXH
tMTXR
tMTXF
TX_EN
TX_ER
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