参数资料
型号: MC8640DHX1250HE
厂商: FREESCALE SEMICONDUCTOR INC
元件分类: 微控制器/微处理器
英文描述: 32-BIT, 1250 MHz, MICROPROCESSOR, CBGA1023
封装: 33 X 33 MM, CERAMIC, FCBGA-1023
文件页数: 7/130页
文件大小: 1495K
代理商: MC8640DHX1250HE
MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 3
104
Freescale Semiconductor
Clocking
18 Clocking
This section describes the PLL configuration of the MPC8640. Note that the platform clock is identical to
the MPX clock.
18.1
Clock Ranges
Table 64 provides the clocking specifications for the processor cores, and Table 65 provides the clocking
specifications for the memory bus. Table 66 provides the clocking for the Platform/MPX bus, and Table 67
provides the clocking for the local bus.
37.This pin is only an output in FIFO mode when used as Rx Flow Control.
38.This pin functions as cfg_dram_type[0 or 1] at reset. Note: This pin must be valid before HRESET assertion in device sleep
mode.
39. Should be pulled to ground if unused (such as in FIFO, MII and RMII modes).
40. See Section 18.4.2, “Platform to FIFO Restrictions” for clock speed limitations for this pin when used in FIFO mode.
41. The phase between the output clocks TSEC1_GTX_CLK and TSEC2_GTX_CLK (ports 1 and 2) is no more than 100 ps.
The phase between the output clocks TSEC3_GTX_CLK and TSEC4_GTX_CLK (ports 3 and 4) is no more than 100 ps.
42. For systems which boot from Local Bus (GPCM)-controlled flash, a pullup on LGPL4 is required.
Special Notes for Single Core Device:
S1. Solder ball for this signal will not be populated in the single core package.
S2. The PLL filter from VDD_Core1 to AVDD_Core1 should be removed. AVDD_Core1 should be pulled to ground with a weak
(2–10 k
Ω) resistor. See Section 20.2.1, “PLL Power Supply Filtering” for more details.
S3. This pin should be pulled to GND for the single core device.
S4. No special requirement for this pin on single core device. Pin should be tied to power supply as directed for dual core.
Table 64. Processor Core Clocking Specifications
Parameter
Maximum Processor Core Frequency
Unit
Notes
1000 MHz
1067 MHz
1250MHz
Min
Max
Min
Max
Min
Max
e600 core processor frequency
800
1000
800
1067
800
1250
MHz
1, 2
Notes:
1. Caution: The MPX clock to SYSCLK ratio and e600 core to MPX clock ratio settings must be chosen such that the resulting
SYSCLK frequency, e600 (core) frequency, and MPX clock frequency do not exceed their respective maximum or minimum
for ratio settings.
2. The minimum e600 core frequency is based on the minimum platform clock frequency of 400 MHz.
Table 63. MPC8640 Signal Reference by Functional Block (continued)
Name1
Package Pin Number
Pin Type
Power Supply
Notes
相关PDF资料
PDF描述
MC8640DHX1067NC 32-BIT, 1067 MHz, MICROPROCESSOR, CBGA1023
MC8640DTVU1000HE 32-BIT, 1000 MHz, MICROPROCESSOR, CBGA1023
MC8640DTHX1067NC 32-BIT, 1067 MHz, MICROPROCESSOR, CBGA1023
MC8640THX1250HC 32-BIT, 1250 MHz, MICROPROCESSOR, CBGA1023
MC8640DTVU1250HE 32-BIT, 1250 MHz, MICROPROCESSOR, CBGA1023
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