参数资料
型号: MC8640DHX1250HE
厂商: FREESCALE SEMICONDUCTOR INC
元件分类: 微控制器/微处理器
英文描述: 32-BIT, 1250 MHz, MICROPROCESSOR, CBGA1023
封装: 33 X 33 MM, CERAMIC, FCBGA-1023
文件页数: 86/130页
文件大小: 1495K
代理商: MC8640DHX1250HE
MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 3
Freescale Semiconductor
59
High-Speed Serial Interfaces (HSSI)
signal is defined as differential peak-to-peak voltage,
VDIFFp-p =2 × VDIFFp =2 × |(A – B)| volts, which is twice of differential swing in
amplitude, or twice of the differential peak. For example, the output differential
peak-peak voltage can also be calculated as VTX-DIFFp-p = 2 × |VOD|.
Differential Waveform
The differential waveform is constructed by subtracting the inverting signal
(SDn_TX, for example) from the non-inverting signal (SDn_TX, for example)
within a differential pair. There is only one signal trace curve in a differential
waveform. The voltage represented in the differential waveform is not referenced
to ground. Refer to Figure 47 as an example for differential waveform.
Common Mode Voltage, Vcm
The common mode voltage is equal to one half of the sum of the voltages between
each conductor of a balanced interchange circuit and ground. In this example, for
SerDes output, Vcm_out = (VSDn_TX + VSDn_TX) ÷ 2 = (A + B) ÷ 2, which is the
arithmetic mean of the two complimentary output voltages within a differential
pair. In a system, the common mode voltage may often differ from one
component’s output to the other’s input. Sometimes, it may be even different
between the receiver input and driver output circuits within the same component.
It is also referred as the DC offset in some occasion.
To illustrate these definitions using real values, consider the case of a current mode logic (CML)
transmitter that has a common mode voltage of 2.25 V and each of its outputs, TD and TD, has a swing
that goes between 2.5 V and 2.0 V. Using these values, the peak-to-peak voltage swing of each signal (TD
or TD) is 500 mV p-p, which is referred as the single-ended swing for each signal. In this example, since
the differential signaling environment is fully symmetrical, the transmitter output’s differential swing
(VOD) has the same amplitude as each signal’s single-ended swing. The differential output signal ranges
between 500 mV and –500 mV, in other words, VOD is 500 mV in one phase and –500 mV in the other
phase. The peak differential voltage (VDIFFp) is 500 mV. The peak-to-peak differential voltage (VDIFFp-p)
is 1000 mV p-p.
13.2
SerDes Reference Clocks
The SerDes reference clock inputs are applied to an internal PLL whose output creates the clock used by
the corresponding SerDes lanes. The SerDes reference clocks inputs are SDn_REF_CLK and
SDn_REF_CLK for PCI Express and Serial RapidIO.
The following sections describe the SerDes reference clock requirements and some application
information.
相关PDF资料
PDF描述
MC8640DHX1067NC 32-BIT, 1067 MHz, MICROPROCESSOR, CBGA1023
MC8640DTVU1000HE 32-BIT, 1000 MHz, MICROPROCESSOR, CBGA1023
MC8640DTHX1067NC 32-BIT, 1067 MHz, MICROPROCESSOR, CBGA1023
MC8640THX1250HC 32-BIT, 1250 MHz, MICROPROCESSOR, CBGA1023
MC8640DTVU1250HE 32-BIT, 1250 MHz, MICROPROCESSOR, CBGA1023
相关代理商/技术参数
参数描述
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MC8640DTHX1000N 制造商:FREESCALE 制造商全称:Freescale Semiconductor, Inc 功能描述:Integrated Host Processor Hardware Specifications Addendum for the MC8640xTxxyyyyaC Series