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参数资料
型号： MC8640DHX1250HE
厂商： FREESCALE SEMICONDUCTOR INC
元件分类： 微控制器/微处理器
英文描述： 32-BIT, 1250 MHz, MICROPROCESSOR, CBGA1023
封装： 33 X 33 MM, CERAMIC, FCBGA-1023
文件页数： 8/130页
文件大小： 1495K
代理商： MC8640DHX1250HE
MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 3
Freescale Semiconductor
105
Clocking
18.2
MPX to SYSCLK PLL Ratio
The MPX clock is the clock that drives the MPX bus, and is also called the platform clock. The frequency
of the MPX is set using the following reset signals, as shown in Table 68:
SYSCLK input signal
Table 65. Memory Bus Clocking Specifications
Parameter
Maximum Processor Core
Frequency
Unit
Notes
1000, 1067, 1250 MHz
Min
Max
Memory bus clock frequency
200
266
MHz
1, 2
Notes:
1. Caution: The MPX clock to SYSCLK ratio and e600 core to MPX clock ratio settings must be chosen such that the resulting
SYSCLK frequency, e600 (core) frequency, and MPX clock frequency do not exceed their respective maximum or minimum
operating frequencies. Refer to Section 18.2, “MPX to SYSCLK PLL Ratio,” and Section 18.3, “e600 to MPX clock PLL Ratio,”
for ratio settings.
2. The memory bus clock speed is half the DDR/DDR2 data rate, hence, half the MPX clock frequency.
Table 66. Platform/MPX bus Clocking Specifications
Parameter
Maximum Processor Core
Frequency
Unit
Notes
1000, 1067, 1250 MHz
Min
Max
Platform/MPX bus clock frequency
400
533
MHz
1, 2
Notes:
1. Caution: The MPX clock to SYSCLK ratio and e600 core to MPX clock ratio settings must be chosen such that the resulting
SYSCLK frequency, e600 (core) frequency, and MPX clock frequency do not exceed their respective maximum or minimum
operating frequencies. Refer to Section 18.2, “MPX to SYSCLK PLL Ratio,” and Section 18.3, “e600 to MPX clock PLL Ratio,”
for ratio settings.
2. Platform/MPX frequencies between 400 and 500 MHz are not supported.
Table 67. Local Bus Clocking Specifications
Parameter
Maximum Processor Core
Frequency
Unit
Notes
1000, 1067, 1250 MHz
Min
Max
Local bus clock speed (for Local Bus Controller)
25
133
MHz
1
Notes:
1. The Local bus clock speed on LCLK[0:2] is determined by MPX clock divided by the Local Bus PLL ratio programmed in
LCRR[CLKDIV]. See the reference manual for the MPC8641D for more information on this.
相关PDF资料
PDF描述
MC8640DHX1067NC 32-BIT, 1067 MHz, MICROPROCESSOR, CBGA1023
MC8640DTVU1000HE 32-BIT, 1000 MHz, MICROPROCESSOR, CBGA1023
MC8640DTHX1067NC 32-BIT, 1067 MHz, MICROPROCESSOR, CBGA1023
MC8640THX1250HC 32-BIT, 1250 MHz, MICROPROCESSOR, CBGA1023
MC8640DTVU1250HE 32-BIT, 1250 MHz, MICROPROCESSOR, CBGA1023
相关代理商/技术参数
参数描述
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