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| 型号： | MCP2030A-I/P |
| 厂商： | Microchip Technology |
| 文件页数： | 38/66页 |
| 文件大小： | 0K |
| 描述： | IC KEYLESS ENTRY AFE 3CH 14PDIP |
| 标准包装： | 30 |
| RF 型： | PEG，TPMS |
| 频率： | 125kHz |
| 特点： | 4 通道 |
| 封装/外壳： | 14-DIP（0.300"，7.62mm） |
| 供应商设备封装： | 14-PDIP |
| 包装： | 管件 |
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MCP2030
TABLE 5-1:
OUTPUT ENABLE FILTER
TIMING
If the filter resets due to a long high-time (T OEH > T OET ),
the high-pulse timer will not begin timing again until
OEH
<1:0>
01
01
01
01
OEL
<1:0>
00
01
10
11
T OEH
(ms)
1
1
1
1
T OEL
(ms)
1
1
2
4
T OET
(ms)
3
3
4
6
after a gap of T E and another low-to-high transition
occurs on the demodulator output.
Disabling the output enable filter disables the T OEH and
T OEL requirement and the device passes all detected
data. See Figure 2-30, Figure 2-31 and Figure 2-32 for
examples.
When viewed from an application perspective, from the
pin input, the actual output enable filter timing must
10
10
10
10
11
11
00
01
10
11
00
01
2
2
2
2
4
4
1
1
2
4
1
1
4
4
5
8
6
6
factor in the analog delays in the input path (such as
demodulator charge and discharge times).
? T OEH - T DR + T DF
? T OEL + T DR - T DF
The output enable filter starts immediately after T GAP ,
the gap after AGC stabilization period.
11
10
4
2
8
5.16
Input Sensitivity Control
11
11
4
4
10
The device has typical input sensitivity of 3 mV PP . This
means any input signal with amplitude greater than 3
00
XX
Filter Disabled
mV PP can be detected. The internal AGC loop regu-
Note 1:
The timing values of T OEH and T OEL are
minimum and T OET is maximum at room
temperature and V DD = 3.0V, 32 kHz
oscillator.
lates the detecting signal amplitude when the input
level is greater than approximately 20 mV PP . This
signal amplitude is called “AGC-active level”. The AGC
loop regulates the input voltage so that the input signal
amplitude range will be kept within the linear range of
T OEH is measured from the rising edge of the
demodulator output to the first falling edge. The pulse
width must fall within T OEH ≤ t ≤ T OET .
T OEL is measured from the falling edge of the
demodulator output to the rising edge of the next pulse.
The pulse width must fall within T OEL ≤ t ≤ T OET .
T OET is measured from rising edge to the next rising
edge (i.e., the sum of T OEH and T OEL ). The sum of T OEH
and T OEL must be t ≤ T OET . If the Configuration Register
0 (Register 5-1), OEH<8:7> is set to ‘ 00 ’, then the filter
is disabled. See Figure 2-30 for this case.
The filter will reset, requiring a complete new successive
high and low period to enable LFDATA, under the
following conditions.
? The received high is not greater than the
configured minimum T OEH value.
? During T OEH , a loss of signal for longer than 56 μ s
causes a filter Reset.
? The received low is not greater than the
configured minimum T OEL value.
? The received sequence exceeds the maximum
T OET value:
- T OEH + T OEL > T OET
- or T OEH > T OET
- or T OEL > T OET
? A Soft Reset SPI command is received.
DS21981A-page 38
the detection circuits without saturation. The AGC
Active Status bit (AGCACT<5>) in STATUS Register 7
(Register 5-8) is set if the AGC loop regulates the input
voltage.
Table 5-2 shows the input sensitivity comparison when
the AGCSIG option is used. When AGCSIG option bit is
set, the demodulated output is available only when the
AGC loop is active (see Table 5-1). The channel input
sensitivity can be reduced by setting the appropriate
Configuration registers. Configuration Register 3
(Register 5-4), Configuration Register 4 (Register 5-5)
and Configuration Register 5 (Register 5-6) have the
option to reduce each channel gain from 0 dB to
approximately -30 dB.
? 2005 Microchip Technology Inc.
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