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参数资料
型号： MCP2030A-I/P
厂商： Microchip Technology
文件页数： 49/66页
文件大小： 0K
描述： IC KEYLESS ENTRY AFE 3CH 14PDIP
标准包装： 30
RF 型： PEG，TPMS
频率： 125kHz
特点： 4 通道
封装/外壳： 14-DIP（0.300"，7.62mm）
供应商设备封装： 14-PDIP
包装： 管件
MCP2030
5.31.2
COMMAND DECODER/
The device operates in SPI mode 0,0. In mode 0,0 the
CONTROLLER
The circuit executes 8 SPI commands from the external
MCU. The command structure is:
Command (3 bits) + Configuration Address (4 bits) +
Data Byte and Row Parity Bit with the Most Significant
bit first. Table 5-5 shows the available SPI commands.
clock idles in the low state (Figure 5-12). SDI data is
loaded into the device on the rising edge of SCLK and
SDO data is clocked out on the falling edge of SCLK.
There must be multiples of 16 clocks (SCLK) while CS
is low or commands will abort.
TABLE 5-5:
SPI COMMANDS
Command Address
Data
Row
Parity
Description
Command only – Address and Data are “Don’t Care”, but need to be clocked in regardless.
000
001
010
011
100
101
XXXX
XXXX
XXXX
XXXX
XXXX
XXXX
XXXX XXXX
XXXX XXXX
XXXX XXXX
XXXX XXXX
XXXX XXXX
XXXX XXXX
X
X
X
X
X
X
Clamp on – enable modulation circuit
Clamp off – disable modulation circuit
Enter Sleep mode (any other command wakes the AFE)
AGC Preserve On – to temporarily preserve the current AGC level
AGC Preserve Off – AGC again tracks strongest input signal
Soft Reset – resets various circuit blocks
Read Command – Data will be read from the specified register address.
110
0000
0001
0010
0011
0100
0101
0110
0111
Config Byte 0
Config Byte 1
Config Byte 2
Config Byte 3
Config Byte 4
Config Byte 5
Column Parity
Status
P
P
P
P
P
P
P
X
General – options that may change during normal operation
LCX antenna tuning and LFDATA output format
LCY antenna tuning
LCZ antenna tuning
LCX and LCY sensitivity reduction
LCZ sensitivity reduction and modulation depth
Column parity byte for Config Byte 0 -> Config Byte 5
Status – parity error, which input is active, etc.
Write Command – Data will be written to the specified register address.
111
0000
0001
0010
0011
0100
0101
0110
0111
Config Byte 0
Config Byte 1
Config Byte 2
Config Byte 3
Config Byte 4
Config Byte 5
Column Parity
Not Used
P
P
P
P
P
P
P
X
Output enable filter, channel enable/disable, etc.
LCX antenna tuning and LFDATA output type
LCY antenna tuning
LCZ antenna tuning
LCX and LCY sensitivity reduction
LCZ sensitivity reduction and modulation depth
Column parity byte for Config Byte 0 -> Config Byte 5
Register is readable, but not writable
Note:
‘P’ denotes the row parity bit (odd parity) for the respective data byte.
? 2005 Microchip Technology Inc.
DS21981A-page 49
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