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参数资料
型号： MCP2030A-I/P
厂商： Microchip Technology
文件页数： 5/66页
文件大小： 0K
描述： IC KEYLESS ENTRY AFE 3CH 14PDIP
标准包装： 30
RF 型： PEG，TPMS
频率： 125kHz
特点： 4 通道
封装/外壳： 14-DIP（0.300"，7.62mm）
供应商设备封装： 14-PDIP
包装： 管件
MCP2030
AC Characteristics (Continued)
Electrical Specifications: Standard Operating Conditions (unless otherwise stated)
Supply Voltage 2.0V ≤ V DD ≤ 3.6V
Operating temperature -40°C ≤ T A ≤ +85°C
LCCOM connected to V SS
LC Signal Input Sinusoidal 300 mV PP
Carrier Frequency 125 kHz
LCCOM connected to V SS
Parameters
Demodulator Discharge Time (delay time
of demodulated output to fall)
Sym.
T DF
Min.
—
Typ?
50
Max.
—
Units
μ s
Conditions
V DD = 3.0V
MOD depth setting = 33%
Input conditions:
Amplitude = 300 mV PP
Modulation depth = 100%
Rise time of LFDATA
Fall time of LFDATA
TR LFDATA
TF LFDATA
—
—
0.5
0.5
—
—
μ s
μ s
V DD = 3.0V. Time is measured from 10% to
90% of amplitude
V DD = 3.0V
Time is measured from 10% to 90% of
amplitude
AGC stabilization time
T STAB
4
—
—
ms
(T AGC + T PAGC )
AGC initialization time
High time after AGC initialization time
Gap time after AGC stabilization time
T AGC
T PAGC
T GAP
—
—
200
3.5
62.5
—
—
—
—
ms
μ s
μ s
Time element of pulse
Time from exiting Sleep or POR to being
T E
T RDY
100
—
—
—
—
50 *
μ s
ms
Minimum pulse width
ready to receive signal
Minimum time AGC level must be held
T PRES
5 *
—
—
ms
AGC level must not change more than 10%
after receiving AGC Preserve command
during T PRES .
Internal RC oscillator frequency
Inactivity timer time-out
Alarm timer time-out
LC Pin Input Resistance for
LCX, LCY, LCZ pins
F OSC
T INACT
T ALARM
R IN
27
13.5
27
—
32
16
32
800*
35.5
17.75
35.5
—
kHz
ms
ms
k Ω
Internal clock trimmed at 32 kHz during test
512 cycles of RC oscillator @ F OSC
1024 cycles of RC oscillator @ F OSC
LCCOM grounded, V DD = 3V,
F CARRIER = 125 kHz.
LC Pin Input Parasitic Capacitance for
C IN
LCCOM grounded, V DD = 3V,
LCX, LCY, LCZ pins
—
24*
—
pF
F CARRIER = 125 kHz.
Minimum output enable filter high time
OEH (Bits Config0<8:7> )
T OEH
RC oscillator = F OSC (see F OSC specification
for variations).
01 = 1 ms
10 = 2 ms
11 = 4 ms
00 = Filter Disabled
32 (~1 ms)
64 (~2 ms)
128 (~4 ms)
—
—
—
—
—
—
—
—
—
clock
count
Viewed from the pin input:
(Note 1)
Minimum output enable filter low time
OEL (Bits Config0<6:5> )
T OEL
RC oscillator = F OSC
Viewed from the pin input:
00 = 1 ms
01 = 1 ms
10 = 2 ms
11 = 4 ms
32 (~1 ms)
32 (~1 ms)
64 (~2 ms)
128 (~4 ms)
—
—
—
—
—
—
—
—
clock
count
(Note 2)
Maximum output enable filter period
T OET
RC oscillator = F OSC
OEH
OEL
T OEH
T OEL
01
01
01
01
00
01
10
11
=
=
=
=
1 ms
1 ms
1 ms
1 ms
1 ms
1 ms
2 ms
4 ms
(Filter 1)
(Filter 1)
(Filter 2)
(Filter 3)
—
—
—
—
—
—
—
—
96 (~3 ms)
96 (~3 ms)
128 (~4 ms)
192 (~6 ms)
10
10
10
10
11
11
11
11
00
01
10
11
00
01
10
11
=
=
=
=
=
=
=
=
2 ms
2 ms
2 ms
2 ms
4 ms
4 ms
4 ms
4 ms
1 ms
1 ms
2 ms
4 ms
1 ms
1 ms
2 ms
4 ms
(Filter 4)
(Filter 4)
(Filter 5)
(Filter 6)
(Filter 7)
(Filter 7)
(Filter 8)
(Filter 9)
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
128 (~4 ms)
128 (~4 ms)
160 (~5 ms)
250 (~8 ms)
192 (~6 ms)
192 (~6 ms)
256 (~8 ms)
320 (~10 ms)
clock
count
00
XX
= Filter Disabled
—
—
—
LFDATA output appears as long as input
signal level is greater than V SENSE .
*
?
Parameter is characterized but not tested.
Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested.
Note
1:
2:
Required output enable filter high time must account for input path analog delays (= T OEH - T DR + T DF ).
Required output enable filter low time must account for input path analog delays (= T OEL + T DR - T DF ).
? 2005 Microchip Technology Inc.
DS21981A-page 5
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