参数资料
型号: MSC7119VM1200
厂商: FREESCALE SEMICONDUCTOR INC
元件分类: 数字信号处理
英文描述: 0-BIT, 300 MHz, OTHER DSP, PBGA400
封装: LEAD FREE, MAPBGA-400
文件页数: 19/60页
文件大小: 1138K
代理商: MSC7119VM1200
MSC7119 Data Sheet, Rev. 8
Electrical Characteristics
Freescale Semiconductor
26
2.5.4
DDR DRAM Controller Timing
This section provides the AC electrical characteristics for the DDR DRAM interface.
2.5.4.1
DDR DRAM Input AC Timing Specifications
Table 17 provides the input AC timing specifications for the DDR DRAM interface.
2.5.4.2
DDR DRAM Output AC Timing Specifications
Table 18 and Table 19 list the output AC timing specifications and measurement conditions for the DDR DRAM
interface.
Table 17. DDR DRAM Input AC Timing
No.
Parameter
Symbol
Min
Max
Unit
AC input low voltage
VIL
—VREF – 0.31
V
AC input high voltage
VIH
VREF + 0.31
VDDM + 0.3
V
201
Maximum Dn input setup skew relative to DQSn input
900
ps
202
Maximum Dn input hold skew relative to DQSn input
900
ps
Notes:
1.
Maximum possible skew between a data strobe (DQSn) and any corresponding bit of data (D[8n + {0...7}] if 0
≤ n ≤ 7).
2.
See Table 18 for tCK value.
3.
Dn should be driven at the same time as DQSn. This is necessary because the DQSn centering on the DQn data tenure is
done internally.
Figure 5. DDR DRAM Input Timing Diagram
Table 18. DDR DRAM Output AC Timing
No.
Parameter
Symbol
Min
Max
Unit
200
CK cycle time, (CK/CK crossing)1
100 MHz (DDR200)
150 MHz (DDR300)
tCK
10
6.67
ns
204
An/RAS/CAS/WE/CKE output setup with respect to CK
tDDKHAS
0.5
× tCK – 1000
ps
205
An/RAS/CAS/WE/CKE output hold with respect to CK
tDDKHAX
0.5
× tCK – 1000
ps
206
CSn output setup with respect to CK
tDDKHCS
0.5
× tCK – 1000
ps
207
CSn output hold with respect to CK
tDDKHCX
0.5
× tCK – 1000
ps
208
CK to DQSn2
tDDKHMH
–600
600
ps
Dn
DQSn
D1
D0
201
202
201
Note: DQS centering is done internally.
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