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参数资料
| 型号： | MSC7119VM1200 |
| 厂商： | FREESCALE SEMICONDUCTOR INC |
| 元件分类： | 数字信号处理 |
| 英文描述： | 0-BIT, 300 MHz, OTHER DSP, PBGA400 |
| 封装： | LEAD FREE, MAPBGA-400 |
| 文件页数： | 43/60页 |
| 文件大小： | 1138K |
| 代理商： | MSC7119VM1200 |
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MSC7119 Data Sheet, Rev. 8
Hardware Design Considerations
Freescale Semiconductor
48
3.2.3
Power Planes
Each power supply pin (VDDC, VDDM, and VDDIO) should have a low-impedance path to the board power supply. Each GND pin
should be provided with a low-impedance path to ground. The power supply pins drive distinct groups of logic on the device.
The MSC7119 VDDC power supply pins should be bypassed to ground using decoupling capacitors. The capacitor leads and
associated printed circuit traces connecting to device power pins and GND should be kept to less than half an inch per capacitor
lead. A minimum four-layer board that employs two inner layers as power and GND planes is recommended. See Section 3.5
for DDR Controller power guidelines.
3.2.4
Decoupling
Both the I/O voltage and core voltage should be decoupled for switching noise. For I/O decoupling, use standard capacitor
values of 0.01
μF for every two to three voltage pins. For core voltage decoupling, use two levels of decoupling. The first level
should consist of a 0.01 F high frequency capacitor with low effective series resistance (ESR) and effective series inductance
(ESL) for every two to three voltage pins. The second decoupling level should consist of two bulk/tantalum decoupling
capacitors, one 10
μF and one 47 μF, (with low ESR and ESL) mounted as closely as possible to the MSC7119 voltage pins.
Additionally, the maximum drop between the power supply and the DSP device should be 15 mV at 1 A.
3.2.5
PLL Power Supply Filtering
The MSC7119 VDDPLL power signal provides power to the clock generation PLL. To ensure stability of the internal clock, the
power supplied to this pin should be filtered with capacitors that have low and high frequency filtering characteristics. VDDPLL
can be connected to VDDC through a 2 Ω resistor. VSSPLL can be tied directly to the GND plane. A circuit similar to the one
shown in Figure 35 is recommended. The PLL loop filter should be placed as closely as possible to the VDDPLL pin (which are
located on the outside edge of the silicon package) to minimize noise coupled from nearby circuits.The 0.01 F capacitor should
be closest to VDDPLL, followed by the 0.1 F capacitor, the 10 F capacitor, and finally the 2-Ω resistor to VDDC. These traces
should be kept short.
3.2.6
Power Consumption
You can reduce power consumption in your design by controlling the power consumption of the following regions of the device:
Extended core. Use the SC1400 Stop and Wait modes by issuing a stop or wait instruction.
Clock synthesis module. Disable the PLL, timer, watchdog, or DDR clocks or disable the CLKO pin.
AHB subsystem. Freeze or shut down the AHB subsystem using the GPSCTL[XBR_HRQ] bit.
Peripheral subsystem. Halt the individual on-device peripherals such as the DDR memory controller, Ethernet MAC,
HDI16, TDM, UART, I2C, and timer modules.
For details, see the “Clocks and Power Management” chapter of the MSC711x Reference Manual.
Figure 35. PLL Power Supply Filter Circuits
VDDC
VDDPLL
2
Ω
0.1 F 0.01 F
10 F
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| MSC711XADS | 功能描述:开发板和工具包 - 其他处理器 DEV SYS FOR FSL 711X DEV RoHS:否 制造商:Freescale Semiconductor 产品:Development Systems 工具用于评估:P3041 核心:e500mc 接口类型:I2C, SPI, USB 工作电源电压: |
| MSC711XEVM | 功能描述:开发板和工具包 - 其他处理器 EVAL KIT W/FULL LIC CW RoHS:否 制造商:Freescale Semiconductor 产品:Development Systems 工具用于评估:P3041 核心:e500mc 接口类型:I2C, SPI, USB 工作电源电压: |
| MSC711XEVMT | 功能描述:KIT EVAL W/FULL LIC CW RoHS:是 类别:编程器，开发系统 >> 过时/停产零件编号 系列:* 标准包装:1 系列:- 传感器类型:CMOS 成像，彩色（RGB） 传感范围:WVGA 接口:I²C 灵敏度:60 fps 电源电压:5.7 V ~ 6.3 V 嵌入式:否 已供物品:成像器板 已用 IC / 零件:KAC-00401 相关产品:4H2099-ND - SENSOR IMAGE WVGA COLOR 48-PQFP4H2094-ND - SENSOR IMAGE WVGA MONO 48-PQFP |
| MSC7121VRF | 制造商:Freescale Semiconductor 功能描述:GPON UMC 140 MHZ - Trays |
| MSC7128 | 制造商:OKI 制造商全称:OKI electronic componets 功能描述:5 x 7-Dot Character x 16-Digit Display Controller/Driver |
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