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参数资料
| 型号： | MSC8112TMP2400V |
| 厂商： | FREESCALE SEMICONDUCTOR INC |
| 元件分类： | 数字信号处理 |
| 英文描述： | OTHER DSP, PBGA431 |
| 封装： | 20 X 20 MM, PLASTIC, BGA-431 |
| 文件页数： | 13/44页 |
| 文件大小： | 1097K |
| 代理商： | MSC8112TMP2400V |
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MSC8112 Dual Core Digital Signal Processor Data Sheet, Rev. 1
Electrical Characteristics
Freescale Semiconductor
20
2.5.4.2
Reset Configuration
The MSC8112 has two mechanisms for writing the reset configuration:
Through the direct slave interface (DSI)
Through the system bus. When the reset configuration is written through the system bus, the MSC8112 acts as a
configuration master or a configuration slave. If configuration slave is selected, but no special configuration word is
written, a default configuration word is applied.
Fourteen signal levels (see Chapter 1 for signal description details) are sampled on PORESET deassertion to define the Reset
Configuration Mode and boot and operating conditions:
RSTCONF
CNFGS
DSISYNC
DSI64
CHIP_ID[0–3]
BM[0–2]
SWTE
MODCK[1–2]
2.5.4.3
Reset Timing Tables
Table 12 and Figure 9 describe the reset timing for a reset configuration write through the direct slave interface (DSI) or
through the system bus.
Table 12. Timing for a Reset Configuration Write through the DSI or System Bus
No.
Characteristics
Expression
Min
Max
Unit
1
Required external PORESET duration minimum
CLKIN = 20 MHz
CLKIN = 100 MHz (300 MHz core)
16/CLKIN
800
160
—
ns
2
Delay from deassertion of external PORESET to deassertion of internal
PORESET
CLKIN = 20 MHz to 100 MHz
1024/CLKIN
6.17
51.2
s
3
Delay from de-assertion of internal PORESET to SPLL lock
CLKIN = 20 MHz (RDF = 1)
CLKIN = 100 MHz (RDF = 1) (300 MHz core)
6400/(CLKIN/RDF)
(PLL reference
clock-division factor)
320
64
320
64
s
5
Delay from SPLL to HRESET deassertion
REFCLK = 40 MHz to 133 MHz
512/REFCLK
3.08
12.8
s
6
Delay from SPLL lock to SRESET deassertion
REFCLK = 40 MHz to 133 MHz
515/REFCLK
3.10
12.88
s
7
Setup time from assertion of
RSTCONF, CNFGS, DSISYNC, DSI64,
CHIP_ID[0–3], BM[0–2], SWTE, and MODCK[1–2] before deassertion of
PORESET
3—
ns
8
Hold time from deassertion of PORESET to deassertion of
RSTCONF,
CNFGS, DSISYNC, DSI64, CHIP_ID[0–3], BM[0–2], SWTE, and
MODCK[1–2]
5—
ns
Note:
Timings are not tested, but are guaranteed by design.
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| MSC8112TVT2400V | 功能描述:DSP DUAL CORE 431-FCPBGA RoHS:是 类别:集成电路 (IC) >> 嵌入式 - DSP（数字式信号处理器） 系列:StarCore 标准包装:2 系列:StarCore 类型:SC140 内核 接口:DSI，以太网，RS-232 时钟速率:400MHz 非易失内存:外部 芯片上RAM:1.436MB 电压 - 输入/输出:3.30V 电压 - 核心:1.20V 工作温度:-40°C ~ 105°C 安装类型:表面贴装 封装/外壳:431-BFBGA，FCBGA 供应商设备封装:431-FCPBGA（20x20） 包装:托盘 |
| MSC8112TVT2400V | 制造商:Freescale Semiconductor 功能描述:Dual Core Digital Signal Processor |
| MSC8113 | 制造商:FREESCALE 制造商全称:Freescale Semiconductor, Inc 功能描述:Tri-Core Digital Signal Processor |
| MSC8113TMP3600V | 功能描述:DSP TRI-CORE 431-FCPBGA RoHS:否 类别:集成电路 (IC) >> 嵌入式 - DSP（数字式信号处理器） 系列:StarCore 标准包装:40 系列:TMS320DM64x, DaVinci™ 类型:定点 接口:I²C，McASP，McBSP 时钟速率:400MHz 非易失内存:外部 芯片上RAM:160kB 电压 - 输入/输出:3.30V 电压 - 核心:1.20V 工作温度:0°C ~ 90°C 安装类型:表面贴装 封装/外壳:548-BBGA，FCBGA 供应商设备封装:548-FCBGA（27x27） 包装:托盘 配用:TMDSDMK642-0E-ND - DEVELPER KIT W/NTSC CAMERA296-23038-ND - DSP STARTER KIT FOR TMS320C6416296-23059-ND - FLASHBURN PORTING KIT296-23058-ND - EVAL MODULE FOR DM642TMDSDMK642-ND - DEVELOPER KIT W/NTSC CAMERA |
| MSC8113TMP4800V | 功能描述:DSP TRI-CORE 431-FCPBGA RoHS:否 类别:集成电路 (IC) >> 嵌入式 - DSP（数字式信号处理器） 系列:StarCore 标准包装:40 系列:TMS320DM64x, DaVinci™ 类型:定点 接口:I²C，McASP，McBSP 时钟速率:400MHz 非易失内存:外部 芯片上RAM:160kB 电压 - 输入/输出:3.30V 电压 - 核心:1.20V 工作温度:0°C ~ 90°C 安装类型:表面贴装 封装/外壳:548-BBGA，FCBGA 供应商设备封装:548-FCBGA（27x27） 包装:托盘 配用:TMDSDMK642-0E-ND - DEVELPER KIT W/NTSC CAMERA296-23038-ND - DSP STARTER KIT FOR TMS320C6416296-23059-ND - FLASHBURN PORTING KIT296-23058-ND - EVAL MODULE FOR DM642TMDSDMK642-ND - DEVELOPER KIT W/NTSC CAMERA |
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