参数资料
型号: MSC8112TMP2400V
厂商: FREESCALE SEMICONDUCTOR INC
元件分类: 数字信号处理
英文描述: OTHER DSP, PBGA431
封装: 20 X 20 MM, PLASTIC, BGA-431
文件页数: 33/44页
文件大小: 1097K
代理商: MSC8112TMP2400V
Hardware Design Considerations
MSC8112 Dual Core Digital Signal Processor Data Sheet, Rev. 1
Freescale Semiconductor
39
Note:
The MSC8112 does not support DLL-enabled mode. For the following two clock schemes, ensure that the DLL is
disabled (that is, the DLLDIS bit in the Hard Reset Configuration Word is set).
If no system synchronization is required (for example, the design does not use SDRAM), you can use any of the
available clock modes.
In the CLKIN synchronization mode, use the following connections:
— Connect the oscillator output through a buffer to CLKIN.
— Connect the CLKIN buffer output to the slave device (for example, SDRAM) making sure that the delay path
between the clock buffer to the MSC8112 and the SDRAM is equal (that is, has a skew less than 100 ps).
— Valid clock modes in this scheme are: 0, 7, 15, 19, 21, 23, 28, 29, 30, and 31.
Note:
See the Clock chapter in the MSC8113 Reference Manual for details.
If the 60x-compatible system bus is not used and SIUMCR[PBSE] is set, PPBS can be disconnected. Otherwise, it
should be pulled up.
The following signals: SWTE, DSISYNC, DSI64, MODCK[1–2], CNFGS, CHIPID[0–3], RSTCONF and BM[0–2] are
used to configure the MSC8112 and are sampled on the deassertion of the PORESET signal. Therefore, they should
be tied to GND or VDDH or through a pull-down or a pull-up resistor until the deassertion of the PORESET signal.
When they are used, INT_OUT (if SIUMCR[INTODC] is cleared), NMI_OUT, and IRQxx (if not full drive) signals must
be pulled up.
When the Ethernet controller is enabled and the SMII mode is selected, GPIO10 and GPIO14 must not be connected
externally to any signal line.
Note:
For details on configuration, see the MSC8112 User’s Guide and MSC8112 Reference Manual. For additional
information, refer to the MSC8113 Design Checklist (ANxxxx).
3.4
External SDRAM Selection
The external bus speed implemented in a system determines the speed of the SDRAM used on that bus. However, because of
differences in timing characteristics among various SDRAM manufacturers, you may have use a faster speed rated SDRAM to
assure efficient data transfer across the bus. For example, for 133 MHz operation, you may have to use 133 or 166 MHz
SDRAM. Always perform a detailed timing analysis using the MSC8112 bus timing values and the manufacturer specifications
for the SDRAM to ensure correct operation within your system design. The output delay listed in SDRAM specifications is
usually given for a load of 30 pF. Scale the number to your specific board load using the typical scaling number provided by
the SDRAM manufacturer.
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