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| 型号： | MSC8112TMP2400V |
| 厂商： | FREESCALE SEMICONDUCTOR INC |
| 元件分类： | 数字信号处理 |
| 英文描述： | OTHER DSP, PBGA431 |
| 封装： | 20 X 20 MM, PLASTIC, BGA-431 |
| 文件页数： | 15/44页 |
| 文件大小： | 1097K |
| 代理商： | MSC8112TMP2400V |
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MSC8112 Dual Core Digital Signal Processor Data Sheet, Rev. 1
Electrical Characteristics
Freescale Semiconductor
22
The UPM machine and GPCM machine outputs change on the internal tick selected by the memory controller configuration.
The AC timing specifications are relative to the internal tick. SDRAM machine outputs change only on the REFCLK rising edge.
Table 14. AC Timing for SIU Inputs
No.
Characteristic
Ref = CLKIN at 1.1 V
and 100 MHz
Units
10
Hold time for all signals after the 50% level of the REFCLK rising edge
0.5
ns
11a
ARTRY/ABB set-up time before the 50% level of the REFCLK rising edge
3.1
ns
11b
DBG/DBB/BG/BR/TC set-up time before the 50% level of the REFCLK rising
edge
3.6
ns
11c
AACK set-up time before the 50% level of the REFCLK rising edge
3.0
ns
11d
TA/TEA/PSDVAL set-up time before the 50% level of the REFCLK rising edge
Data-pipeline mode
Non-pipeline mode
3.5
4.4
ns
12
Data bus set-up time before REFCLK rising edge in Normal mode
Data-pipeline mode
Non-pipeline mode
1.9
4.2
ns
131
Data bus set-up time before the 50% level of the REFCLK rising edge in ECC
and PARITY modes
Data-pipeline mode
Non-pipeline mode
2.0
8.2
ns
141
DP set-up time before the 50% level of the REFCLK rising edge
Data-pipeline mode
Non-pipeline mode
2.0
7.9
ns
15a
TS and Address bus set-up time before the 50% level of the REFCLK rising edge
Extra cycle mode (SIUBCR[EXDD] = 0)
No extra cycle mode (SIUBCR[EXDD] = 1)
4.2
5.5
ns
15b
Address attributes: TT/TBST/TSZ/GBL set-up time before the 50% level of the
REFCLK rising edge
Extra cycle mode (SIUBCR[EXDD] = 0)
No extra cycle mode (SIUBCR[EXDD] = 1)
3.7
4.8
ns
16
PUPMWAIT signal set-up time before the 50% level of the REFCLK rising edge
3.7
ns
17
IRQx setup time before the 50% level; of the REFCLK rising edge3
4.0
ns
18
IRQx minimum pulse width3
6.0 + TREFCLK
ns
Notes:
1.
Timings specifications 13 and 14 in non-pipeline mode are more restrictive than MSC8102 timings.
2.
Values are measured from the 50% TTL transition level relative to the 50% level of the REFCLK rising edge.
3.
Guaranteed by design.
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相关代理商/技术参数 |
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| MSC8112TVT2400V | 功能描述:DSP DUAL CORE 431-FCPBGA RoHS:是 类别:集成电路 (IC) >> 嵌入式 - DSP（数字式信号处理器） 系列:StarCore 标准包装:2 系列:StarCore 类型:SC140 内核 接口:DSI，以太网，RS-232 时钟速率:400MHz 非易失内存:外部 芯片上RAM:1.436MB 电压 - 输入/输出:3.30V 电压 - 核心:1.20V 工作温度:-40°C ~ 105°C 安装类型:表面贴装 封装/外壳:431-BFBGA，FCBGA 供应商设备封装:431-FCPBGA（20x20） 包装:托盘 |
| MSC8112TVT2400V | 制造商:Freescale Semiconductor 功能描述:Dual Core Digital Signal Processor |
| MSC8113 | 制造商:FREESCALE 制造商全称:Freescale Semiconductor, Inc 功能描述:Tri-Core Digital Signal Processor |
| MSC8113TMP3600V | 功能描述:DSP TRI-CORE 431-FCPBGA RoHS:否 类别:集成电路 (IC) >> 嵌入式 - DSP（数字式信号处理器） 系列:StarCore 标准包装:40 系列:TMS320DM64x, DaVinci™ 类型:定点 接口:I²C，McASP，McBSP 时钟速率:400MHz 非易失内存:外部 芯片上RAM:160kB 电压 - 输入/输出:3.30V 电压 - 核心:1.20V 工作温度:0°C ~ 90°C 安装类型:表面贴装 封装/外壳:548-BBGA，FCBGA 供应商设备封装:548-FCBGA（27x27） 包装:托盘 配用:TMDSDMK642-0E-ND - DEVELPER KIT W/NTSC CAMERA296-23038-ND - DSP STARTER KIT FOR TMS320C6416296-23059-ND - FLASHBURN PORTING KIT296-23058-ND - EVAL MODULE FOR DM642TMDSDMK642-ND - DEVELOPER KIT W/NTSC CAMERA |
| MSC8113TMP4800V | 功能描述:DSP TRI-CORE 431-FCPBGA RoHS:否 类别:集成电路 (IC) >> 嵌入式 - DSP（数字式信号处理器） 系列:StarCore 标准包装:40 系列:TMS320DM64x, DaVinci™ 类型:定点 接口:I²C，McASP，McBSP 时钟速率:400MHz 非易失内存:外部 芯片上RAM:160kB 电压 - 输入/输出:3.30V 电压 - 核心:1.20V 工作温度:0°C ~ 90°C 安装类型:表面贴装 封装/外壳:548-BBGA，FCBGA 供应商设备封装:548-FCBGA（27x27） 包装:托盘 配用:TMDSDMK642-0E-ND - DEVELPER KIT W/NTSC CAMERA296-23038-ND - DSP STARTER KIT FOR TMS320C6416296-23059-ND - FLASHBURN PORTING KIT296-23058-ND - EVAL MODULE FOR DM642TMDSDMK642-ND - DEVELOPER KIT W/NTSC CAMERA |
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