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参数资料
| 型号： | MSC8112TMP2400V |
| 厂商： | FREESCALE SEMICONDUCTOR INC |
| 元件分类： | 数字信号处理 |
| 英文描述： | OTHER DSP, PBGA431 |
| 封装： | 20 X 20 MM, PLASTIC, BGA-431 |
| 文件页数： | 16/44页 |
| 文件大小： | 1097K |
| 代理商： | MSC8112TMP2400V |
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Electrical Characteristics
MSC8112 Dual Core Digital Signal Processor Data Sheet, Rev. 1
Freescale Semiconductor
23
Table 15. AC Timing for SIU Outputs
No.
Characteristic
Bus Speed in MHz3
Ref = CLKIN at 1.1 V
and 100 MHz
Units
302
Minimum delay from the 50% level of the REFCLK for all signals
0.9
ns
31
PSDVAL/TEA/TA max delay from the 50% level of the REFCLK rising edge
6.0
ns
32a
Address bus max delay from the 50% level of the REFCLK rising edge
Multi-master mode (SIUBCR[EBM] = 1)
Single-master mode (SIUBCR[EBM] = 0)
6.4
5.3
ns
32b
Address attributes: TT[0–1]/TBST/TSZ/GBL max delay from the 50% level
of the REFCLK rising edge
6.4
ns
32c
Address attributes: TT[2–4]/TC max delay from the 50% level of the
REFCLK rising edge
6.9
ns
32d
BADDR max delay from the 50% level of the REFCLK rising edge
5.2
ns
33a
Data bus max delay from the 50% level of the REFCLK rising edge
Data-pipeline mode
Non-pipeline mode
4.8
7.1
ns
33b
DP max delay from the 50% level of the REFCLK rising edge
Data-pipeline mode
Non-pipeline mode
6.0
7.5
ns
34
Memory controller signals/ALE/CS[0–4] max delay from the 50% level of
the REFCLK rising edge
5.1
ns
35a
DBG/BG/BR/DBB max delay from the 50% level of the REFCLK rising
edge
6.0
ns
35b
AACK/ABB/TS/CS[5–7] max delay from the 50% level of the REFCLK
rising edge
5.5
ns
Notes:
1.
Values are measured from the 50% level of the REFCLK rising edge to the 50% signal level and assume a 20 pF load except
where otherwise specified.
2.
Except for specification 30, which is specified for a 10 pF load, all timings in this table are specified for a 20 pF load.
Decreasing the load results in a timing decrease at the rate of 0.3 ns per 5 pF decrease in load. Increasing the load results in
a timing increase at the rate of 0.15 ns per 5 pF increase in load.
3.
The maximum bus frequency depends on the mode:
In 60x-compatible mode connected to another MSC8112 device, the frequency is determined by adding the input and output
longest timing values, which results in the total delay for 20 pF output capacitance. You must also account for other
influences that can affect timing, such as on-board clock skews, on-board noise delays, and so on.
In single-master mode, the frequency depends on the timing of the devices connected to the MSC8112.
To achieve maximum performance on the bus in single-master mode, disable the DBB signal by writing a 1 to the
SIUMCR[BDD] bit. See the SIU chapter in the MSC8112 Reference Manual for details.
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相关代理商/技术参数 |
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| MSC8112TVT2400V | 功能描述:DSP DUAL CORE 431-FCPBGA RoHS:是 类别:集成电路 (IC) >> 嵌入式 - DSP（数字式信号处理器） 系列:StarCore 标准包装:2 系列:StarCore 类型:SC140 内核 接口:DSI，以太网，RS-232 时钟速率:400MHz 非易失内存:外部 芯片上RAM:1.436MB 电压 - 输入/输出:3.30V 电压 - 核心:1.20V 工作温度:-40°C ~ 105°C 安装类型:表面贴装 封装/外壳:431-BFBGA，FCBGA 供应商设备封装:431-FCPBGA（20x20） 包装:托盘 |
| MSC8112TVT2400V | 制造商:Freescale Semiconductor 功能描述:Dual Core Digital Signal Processor |
| MSC8113 | 制造商:FREESCALE 制造商全称:Freescale Semiconductor, Inc 功能描述:Tri-Core Digital Signal Processor |
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| MSC8113TMP4800V | 功能描述:DSP TRI-CORE 431-FCPBGA RoHS:否 类别:集成电路 (IC) >> 嵌入式 - DSP（数字式信号处理器） 系列:StarCore 标准包装:40 系列:TMS320DM64x, DaVinci™ 类型:定点 接口:I²C，McASP，McBSP 时钟速率:400MHz 非易失内存:外部 芯片上RAM:160kB 电压 - 输入/输出:3.30V 电压 - 核心:1.20V 工作温度:0°C ~ 90°C 安装类型:表面贴装 封装/外壳:548-BBGA，FCBGA 供应商设备封装:548-FCBGA（27x27） 包装:托盘 配用:TMDSDMK642-0E-ND - DEVELPER KIT W/NTSC CAMERA296-23038-ND - DSP STARTER KIT FOR TMS320C6416296-23059-ND - FLASHBURN PORTING KIT296-23058-ND - EVAL MODULE FOR DM642TMDSDMK642-ND - DEVELOPER KIT W/NTSC CAMERA |
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