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参数资料
| 型号： | MSC8112TMP2400V |
| 厂商： | FREESCALE SEMICONDUCTOR INC |
| 元件分类： | 数字信号处理 |
| 英文描述： | OTHER DSP, PBGA431 |
| 封装： | 20 X 20 MM, PLASTIC, BGA-431 |
| 文件页数： | 31/44页 |
| 文件大小： | 1097K |
| 代理商： | MSC8112TMP2400V |
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Hardware Design Considerations
MSC8112 Dual Core Digital Signal Processor Data Sheet, Rev. 1
Freescale Semiconductor
37
During the power-up sequence, if VDD rises before VDDH (see Figure 6), current can pass from the VDD supply through the
device ESD protection circuits to the VDDH supply. The ESD protection diode can allow this to occur when VDD exceeds VDDH
by more than 0.8 V. Design the power supply to prevent or minimize this effect using one of the following optional methods:
Never allow VDD to exceed VDDH + 0.8V.
Design the VDDH supply to prevent reverse current flow by adding a minimum 10 Ω resistor to GND to limit the
current. Such a design yields an initial VDDH level of VDD – 0.8 V before it is enabled.
After power-up, VDDH must not exceed VDD/VCCSYN by more than 2.6 V.
3.2
When implementing a new design, use the guidelines described in the MSC8112 Design Checklist (AN3374 for optimal system
performance. MSC8122 and MSC8126 Power Circuit Design Recommendations and Examples (AN2937) provides detailed
design information. See Section 2.5.2 for start-up timing specifications.
Figure 33 shows the recommended power decoupling circuit for the core power supply. The voltage regulator and the
decoupling capacitors should supply the required device current without any drop in voltage on the device pins. The voltage on
the package pins should not drop below the minimum specified voltage level even for a very short spikes. This can be achieved
by using the following guidelines:
For the core supply, use a voltage regulator rated at 1.1 V with nominal rating of at least 3 A. This rating does not
reflect actual average current draw, but is recommended because it resists changes imposed by transient spikes and has
better voltage recovery time than supplies with lower current ratings.
Decouple the supply using low-ESR capacitors mounted as close as possible to the socket. Figure 33 shows three
capacitors in parallel to reduce the resistance. Three capacitors is a recommended minimum number. If possible, mount
at least one of the capacitors directly below the MSC8112 device.
Each VCC and VDD pin on the MSC8112 device should have a low-impedance path to the board power supply. Similarly, each
GND
pin should have a low-impedance path to the ground plane. The power supply pins drive distinct groups of logic on the
chip. The VCC power supply should have at least four 0.1 F by-pass capacitors to ground located as closely as possible to the
four sides of the package. The capacitor leads and associated printed circuit traces connecting to chip VCC, VDD, and GND should
be kept to less than half an inch per capacitor lead. A four-layer board is recommended, employing two inner layers as VCC and
GND
planes.
All output pins on the MSC8112 have fast rise and fall times. PCB trace interconnection length should be minimized to
minimize undershoot and reflections caused by these fast output switching times. This recommendation particularly applies to
the address and data buses. Maximum PCB trace lengths of six inches are recommended. For the DSI control signals in
synchronous mode, ensure that the layout supports the DSI AC timing requirements and minimizes any signal crosstalk.
Capacitance calculations should consider all device loads as well as parasitic capacitances due to the PCB traces. Attention to
proper PCB layout and bypassing becomes especially critical in systems with higher capacitive loads because these loads create
higher transient currents in the VCC, VDD, and GND circuits. Pull up all unused inputs or signals that will be inputs during reset.
Figure 33. Core Power Supply Decoupling
+
-
Power supply
or
Voltage Regulator
High frequency capacitors
(very low ESR and ESL)
Bulk/Tantalum capacitors
with low ESR and ESL
MSC8113
Maximum IR drop
of 15 mV at 1 A
Note: Use at least three capacitors.
Lmax = 2 cm
One 0.01 F capacitor
for every 3 core supply
(Imin = 3 A)
pads.
1.1 V
Each capacitor must be at least 150
μF.
相关PDF资料 |
PDF描述 |
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| MSC81250M | L BAND, Si, NPN, RF POWER TRANSISTOR |
| MSC81250M | L BAND, Si, NPN, RF POWER TRANSISTOR |
| MSC81402 | L BAND, Si, NPN, RF SMALL SIGNAL TRANSISTOR |
| MSC81450M | L BAND, Si, NPN, RF POWER TRANSISTOR |
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相关代理商/技术参数 |
参数描述 |
|---|---|
| MSC8112TVT2400V | 功能描述:DSP DUAL CORE 431-FCPBGA RoHS:是 类别:集成电路 (IC) >> 嵌入式 - DSP（数字式信号处理器） 系列:StarCore 标准包装:2 系列:StarCore 类型:SC140 内核 接口:DSI，以太网，RS-232 时钟速率:400MHz 非易失内存:外部 芯片上RAM:1.436MB 电压 - 输入/输出:3.30V 电压 - 核心:1.20V 工作温度:-40°C ~ 105°C 安装类型:表面贴装 封装/外壳:431-BFBGA，FCBGA 供应商设备封装:431-FCPBGA（20x20） 包装:托盘 |
| MSC8112TVT2400V | 制造商:Freescale Semiconductor 功能描述:Dual Core Digital Signal Processor |
| MSC8113 | 制造商:FREESCALE 制造商全称:Freescale Semiconductor, Inc 功能描述:Tri-Core Digital Signal Processor |
| MSC8113TMP3600V | 功能描述:DSP TRI-CORE 431-FCPBGA RoHS:否 类别:集成电路 (IC) >> 嵌入式 - DSP（数字式信号处理器） 系列:StarCore 标准包装:40 系列:TMS320DM64x, DaVinci™ 类型:定点 接口:I²C，McASP，McBSP 时钟速率:400MHz 非易失内存:外部 芯片上RAM:160kB 电压 - 输入/输出:3.30V 电压 - 核心:1.20V 工作温度:0°C ~ 90°C 安装类型:表面贴装 封装/外壳:548-BBGA，FCBGA 供应商设备封装:548-FCBGA（27x27） 包装:托盘 配用:TMDSDMK642-0E-ND - DEVELPER KIT W/NTSC CAMERA296-23038-ND - DSP STARTER KIT FOR TMS320C6416296-23059-ND - FLASHBURN PORTING KIT296-23058-ND - EVAL MODULE FOR DM642TMDSDMK642-ND - DEVELOPER KIT W/NTSC CAMERA |
| MSC8113TMP4800V | 功能描述:DSP TRI-CORE 431-FCPBGA RoHS:否 类别:集成电路 (IC) >> 嵌入式 - DSP（数字式信号处理器） 系列:StarCore 标准包装:40 系列:TMS320DM64x, DaVinci™ 类型:定点 接口:I²C，McASP，McBSP 时钟速率:400MHz 非易失内存:外部 芯片上RAM:160kB 电压 - 输入/输出:3.30V 电压 - 核心:1.20V 工作温度:0°C ~ 90°C 安装类型:表面贴装 封装/外壳:548-BBGA，FCBGA 供应商设备封装:548-FCBGA（27x27） 包装:托盘 配用:TMDSDMK642-0E-ND - DEVELPER KIT W/NTSC CAMERA296-23038-ND - DSP STARTER KIT FOR TMS320C6416296-23059-ND - FLASHBURN PORTING KIT296-23058-ND - EVAL MODULE FOR DM642TMDSDMK642-ND - DEVELOPER KIT W/NTSC CAMERA |
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