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参数资料
| 型号： | MT46H256M32L4CM-54IT:A |
| 元件分类： | DRAM |
| 英文描述： | 256M X 32 DDR DRAM, 5 ns, PBGA90 |
| 封装： | 10 X 13 MM, GREEN, PLASTIC, VFBGA-90 |
| 文件页数： | 3/106页 |
| 文件大小： | 3431K |
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Figure 58: Self Refresh Mode
CK1
CK#
Command
NOP
AR3
Address
CKE1,2
Valid
DQ
DM
DQS
Valid
NOP
tRP4
tCH
tCL
tCK
tIS
tXSR5
tIS
tIH
tIS
tIS tIH
tIS
Enter self refresh mode
Exit self refresh mode
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T0
T1
Tb0
Ta1
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Don’t Care
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Ta01
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tCKE
Notes: 1. Clock must be stable, cycling within specifications by Ta0, before exiting self refresh mode.
2. CKE must remain LOW to remain in self refresh.
3. AR = AUTO REFRESH.
4. Device must be in the all banks idle state prior to entering self refresh mode.
5. Either a NOP or DESELECT command is required for tXSR time with at least two clock pulses.
Power-Down
Power-down is entered when CKE is registered LOW. If power-down occurs when all
banks are idle, this mode is referred to as precharge power-down; if power-down occurs
when there is a row active in any bank, this mode is referred to as active power-down.
Entering power-down deactivates all input and output buffers, including CK and CK#
and excluding CKE. Exiting power-down requires the device to be at the same voltage as
when it entered power-down and received a stable clock. Note that the power-down
duration is limited by the refresh requirements of the device.
When in power-down, CKE LOW must be maintained at the inputs of the device, while
all other input signals are “Don’t Care.” The power-down state is synchronously exited
when CKE is registered HIGH (in conjunction with a NOP or DESELECT command).
NOP or DESELECT commands must be maintained on the command bus until tXP is
satisfied. See Figure 60 (page 102) for a detailed illustration of power-down mode.
2Gb: x16, x32 Mobile LPDDR SDRAM
Power-Down
PDF: 09005aef83a73286
2gb_ddr_mobile_sdram_t69m.pdf - Rev. M 11/10 EN
100
Micron Technology, Inc. reserves the right to change products or specifications without notice.
2009 Micron Technology, Inc. All rights reserved.
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