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参数资料
| 型号： | MT46H256M32L4CM-54IT:A |
| 元件分类： | DRAM |
| 英文描述： | 256M X 32 DDR DRAM, 5 ns, PBGA90 |
| 封装： | 10 X 13 MM, GREEN, PLASTIC, VFBGA-90 |
| 文件页数： | 72/106页 |
| 文件大小： | 3431K |
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Bank/Row Activation
Before any READ or WRITE commands can be issued to a bank within the device, a row
in that bank must be opened. This is accomplished via the ACTIVE command, which
selects both the bank and the row to be activated (see Figure 18 (page 46)). After a row is
opened with the ACTIVE command, a READ or WRITE command can be issued to that
row, subject to the tRCD specification.
A subsequent ACTIVE command to a different row in the same bank can only be issued
after the previous active row has been precharged. The minimum time interval between
successive ACTIVE commands to the same bank is defined by tRC.
A subsequent ACTIVE command to another bank can be issued while the first bank is
being accessed, which results in a reduction of total row access overhead. The mini-
mum time interval between successive ACTIVE commands to different banks is defined
by tRRD.
2Gb: x16, x32 Mobile LPDDR SDRAM
Bank/Row Activation
PDF: 09005aef83a73286
2gb_ddr_mobile_sdram_t69m.pdf - Rev. M 11/10 EN
68
Micron Technology, Inc. reserves the right to change products or specifications without notice.
2009 Micron Technology, Inc. All rights reserved.
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