参数资料
型号: MT46H256M32L4CM-54IT:A
元件分类: DRAM
英文描述: 256M X 32 DDR DRAM, 5 ns, PBGA90
封装: 10 X 13 MM, GREEN, PLASTIC, VFBGA-90
文件页数: 82/106页
文件大小: 3431K
Figure 38: Data Output Timing – tDQSQ, tQH, and Data Valid Window (x16)
DQ (Last data valid)4
DQ4
LDQS3
DQ (Last data valid)4
DQ (First data no longer valid)4
DQ[7:0] and LDQS, collectively6
T2
T2n
T3
T3n
CK
CK#
T1
T2
T3
T4
T2n
T3n
tQH5
tDQSQ2
Data valid
window
Data valid
window
DQ (Last data valid)7
DQ7
UDQS3
DQ (Last data valid)7
DQ (First data no longer valid)7
DQ[15:8] and UDQS, collectively6
T2
T2n
T3
T3n
tQH5
tDQSQ2
tHP1
tQH5
Data valid
window
Data valid
window
Data valid
window
Data valid
window
Data valid
window
Upper
Byte
Lower
Byte
Data valid
window
Notes: 1. tHP is the lesser of tCL or tCH clock transition collectively when a bank is active.
2. tDQSQ is derived at each DQS clock edge and is not cumulative over time and begins
with DQS transition and ends with the last valid DQ transition.
3. DQ transitioning after DQS transitions define the tDQSQ window. LDQS defines the low-
er byte and UDQS defines the upper byte.
4. DQ0, DQ1, DQ2, DQ3, DQ4, DQ5, DQ6, or DQ7.
5. tQH is derived from tHP: tQH = tHP - tQHS.
6. The data valid window is derived for each DQS transitions and is defined as tQH - tDQSQ.
7. DQ8, DQ9, DQ10, DQ11, DQ12, DQ13, DQ14, or DQ15.
2Gb: x16, x32 Mobile LPDDR SDRAM
READ Operation
PDF: 09005aef83a73286
2gb_ddr_mobile_sdram_t69m.pdf - Rev. M 11/10 EN
77
Micron Technology, Inc. reserves the right to change products or specifications without notice.
2009 Micron Technology, Inc. All rights reserved.
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