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参数资料
| 型号： | MT46H128M32L2JV-54AT:A |
| 元件分类： | DRAM |
| 英文描述： | 128M X 32 DDR DRAM, 5 ns, PBGA168 |
| 封装： | 12 X 12 MM, GREEN, PLASTIC, VFBGA-168 |
| 文件页数： | 1/106页 |
| 文件大小： | 3431K |
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Mobile Low-Power DDR SDRAM
MT46H128M16LF – 32 Meg x 16 x 4 Banks
MT46H64M32LF – 16 Meg x 32 x 4 Banks
MT46H128M32L2 – 16 Meg x 32 x 4 Banks x 2
MT46H256M32L4 – 32 Meg x 16 x 4 Banks x 4
MT46H256M32R4 – 32 Meg x 16 x 4 Banks x 4
Features
VDD/VDDQ = 1.70–1.95V
Bidirectional data strobe per byte of data (DQS)
Internal, pipelined double data rate (DDR)
architecture; two data accesses per clock cycle
Differential clock inputs (CK and CK#)
Commands entered on each positive CK edge
DQS edge-aligned with data for READs; center-
aligned with data for WRITEs
4 internal banks for concurrent operation
Data masks (DM) for masking write data; one mask
per byte
Programmable burst lengths (BL): 2, 4, 8, or 16
Concurrent auto precharge option is supported
Auto refresh and self refresh modes
1.8V LVCMOS-compatible inputs
Temperature-compensated self refresh (TCSR)
Partial-array self refresh (PASR)
Deep power-down (DPD)
Status read register (SRR)
Selectable output drive strength (DS)
Clock stop capability
64ms refresh; 32ms for the automotive temperature
range
Table 1: Key Timing Parameters (CL = 3)
Speed Grade
Clock Rate
Access Time
-5
200 MHz
5.0ns
-54
185 MHz
5.0ns
-6
166 MHz
5.0ns
-75
133 MHz
6.0ns
Options
Marking
VDD/VDDQ
– 1.8V/1.8V
H
Configuration
– 128 Meg x 16 (32 Meg x 16 x 4 banks) 128M16
– 64 Meg x 32 (16 Meg x 32 x 4 banks)
64M32
Addressing
– JEDEC-standard
LF
– Reduced page-size1
LG
– 4-die stack reduced page-size2
R4
– 2-die stack standard
L2
– 4-die stack standard
L4
Plastic "green" package
– 60-ball VFBGA (10mm x 11.5mm)3
CK
– 90-ball VFBGA (10mm x 13mm)4
CM
PoP (plastic "green" package)
– 168-ball VFBGA (12mm x 12mm)4
JV
– 168-ball WFBGA (12mm x 12mm)4
KQ
– 168-ball WFBGA (12mm x 12mm)4
MA
– 240-ball WFBGA (14mm x 14mm)4
MC
Timing – cycle time
– 5ns @ CL = 3 (200 MHz)
-5
– 5.4ns @ CL = 3 (185 MHz)
-54
– 6ns @ CL = 3 (166 MHz)
-6
– 7.5ns @ CL = 3 (133 MHz)
-75
Power
– Standard IDD2/IDD6
None
Operating temperature range
– Commercial (0 to +70C)
None
– Industrial (–40C to +85C)
IT
– Automotive (–40C to +105C)1
AT
Design revision
:A
Notes: 1. Contact factory for availability.
2. Available in the 168-ball JV package only.
3. Available only for x16 configuration.
4. Available only for x32 configuration.
2Gb: x16, x32 Mobile LPDDR SDRAM
Features
PDF: 09005aef83a73286
2gb_ddr_mobile_sdram_t69m.pdf - Rev. M 11/10 EN
1
Micron Technology, Inc. reserves the right to change products or specifications without notice.
2009 Micron Technology, Inc. All rights reserved.
Products and specifications discussed herein are subject to change by Micron without notice.
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