参数资料
型号: MT46H128M32L2JV-54AT:A
元件分类: DRAM
英文描述: 128M X 32 DDR DRAM, 5 ns, PBGA168
封装: 12 X 12 MM, GREEN, PLASTIC, VFBGA-168
文件页数: 57/106页
文件大小: 3431K
executed with auto precharge disabled and then followed with the earliest possible PRE-
CHARGE command that still accesses all of the data in the burst. For write with auto
precharge, the precharge period begins when tWR ends, with tWR measured as if auto
precharge was disabled. The access period starts with registration of the command and
ends when the precharge period (or tRP) begins. This device supports concurrent auto
precharge such that when a read with auto precharge is enabled or a write with auto
precharge is enabled, any command to other banks is supported, as long as that com-
mand does not interrupt the read or write data transfer already in process. In either
case, all other related limitations apply (i.e., contention between read data and write
data must be avoided).
3b. The minimum delay from a READ or WRITE command (with auto precharge enabled)
to a command to a different bank is summarized below.
From
Command
To Command
Minimum Delay
(with Concurrent Auto
Precharge)
WRITE with
Auto Precharge
READ or READ with auto precharge
WRITE or WRITE with auto precharge
PRECHARGE
ACTIVE
[1 + (BL/2)] tCK + tWTR
(BL/2) tCK
1 tCK
READ with
Auto Precharge
READ or READ with auto precharge
WRITE or WRITE with auto precharge
PRECHARGE
ACTIVE
(BL/2) × tCK
[CL + (BL/2)] tCK
1 tCK
4. AUTO REFRESH and LOAD MODE REGISTER commands can only be issued when all
banks are idle.
5. All states and sequences not shown are illegal or reserved.
6. Requires appropriate DM masking.
7. A WRITE command can be applied after the completion of the READ burst; otherwise, a
BURST TERMINATE must be used to end the READ burst prior to asserting a WRITE com-
mand.
2Gb: x16, x32 Mobile LPDDR SDRAM
Truth Tables
PDF: 09005aef83a73286
2gb_ddr_mobile_sdram_t69m.pdf - Rev. M 11/10 EN
54
Micron Technology, Inc. reserves the right to change products or specifications without notice.
2009 Micron Technology, Inc. All rights reserved.
相关PDF资料
PDF描述
MT46H128M32L4CM-5AT:A 128M X 32 DDR DRAM, 5 ns, PBGA90
MT46H128M32L4KQ-75:A 128M X 32 DDR DRAM, 6 ns, PBGA168
MT46H128M32L4MA-54:A 128M X 32 DDR DRAM, 5 ns, PBGA168
MT46H128M32LFCM-5AT:A 128M X 32 DDR DRAM, 5 ns, PBGA90
MT46H128M32LFCM-5IT:A 128M X 32 DDR DRAM, 5 ns, PBGA90
相关代理商/技术参数
参数描述