- 您现在的位置：买卖IC网 > PDF目录296642 > MT46H128M32L2JV-54AT:A 128M X 32 DDR DRAM, 5 ns, PBGA168 PDF资料下载
参数资料
| 型号： | MT46H128M32L2JV-54AT:A |
| 元件分类： | DRAM |
| 英文描述： | 128M X 32 DDR DRAM, 5 ns, PBGA168 |
| 封装： | 12 X 12 MM, GREEN, PLASTIC, VFBGA-168 |
| 文件页数： | 66/106页 |
| 文件大小： | 3431K |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页第39页第40页第41页第42页第43页第44页第45页第46页第47页第48页第49页第50页第51页第52页第53页第54页第55页第56页第57页第58页第59页第60页第61页第62页第63页第64页第65页当前第66页第67页第68页第69页第70页第71页第72页第73页第74页第75页第76页第77页第78页第79页第80页第81页第82页第83页第84页第85页第86页第87页第88页第89页第90页第91页第92页第93页第94页第95页第96页第97页第98页第99页第100页第101页第102页第103页第104页第105页第106页
Table 21: Burst Definition Table (Continued)
Burst
Length
Starting Column Address
Order of Accesses Within a Burst
Type = Sequential
Type = Interleaved
0
0-1-2-3-4-5-6-7-8-9-A-B-C-D-E-F
0
1
1-2-3-4-5-6-7-8-9-A-B-C-D-E-F-0
1-0-3-2-5-4-7-6-9-8-B-A-D-C-F-E
0
1
0
2-3-4-5-6-7-8-9-A-B-C-D-E-F-0-1
2-3-0-1-6-7-4-5-A-B-8-9-E-F-C-D
0
1
3-4-5-6-7-8-9-A-B-C-D-E-F-0-1-2
3-2-1-0-7-6-5-4-B-A-9-8-F-E-D-C
0
1
0
4-5-6-7-8-9-A-B-C-D-E-F-0-1-2-3
4-5-6-7-0-1-2-3-C-D-E-F-8-9-A-B
0
1
0
1
5-6-7-8-9-A-B-C-D-E-F-0-1-2-3-4
5-4-7-6-1-0-3-2-D-C-F-E-9-8-B-A
0
1
0
6-7-8-9-A-B-C-D-E-F-0-1-2-3-4-5
6-7-4-5-2-3-0-1-E-F-C-D-A-B-8-9
0
1
7-8-9-A-B-C-D-E-F-0-1-2-3-4-5-6
7-6-5-4-3-2-1-0-F-E-D-C-B-A-9-8
1
0
8-9-A-B-C-D-E-F-0-1-2-3-4-5-6-7
1
0
1
9-A-B-C-D-E-F-0-1-2-3-4-5-6-7-8
9-8-B-A-D-C-F-E-1-0-3-2-5-4-7-6
1
0
1
0
A-B-C-D-E-F-0-1-2-3-4-5-6-7-8-9
A-B-8-9-E-F-C-D-2-3-0-1-6-7-4-5
1
0
1
B-C-D-E-F-0-1-2-3-4-5-6-7-8-9-A
B-A-9-8-F-E-D-C-3-2-1-0-7-6-5-4
1
0
C-D-E-F-0-1-2-3-4-5-6-7-8-9-A-B
C-D-E-F-8-9-A-B-4-5-6-7-0-1-2-3
1
0
1
D-E-F-0-1-2-3-4-5-6-7-8-9-A-B-C
D-C-F-E-9-8-B-A-5-4-7-6-1-0-3-2
1
0
E-F-0-1-2-3-4-5-6-7-8-9-A-B-C-D
E-F-C-D-A-B-8-9-6-7-4-5-2-3-0-1
1
F-0-1-2-3-4-5-6-7-8-9-A-B-C-D-E
F-E-D-C-B-A-9-8-7-6-5-4-3-2-1-0
CAS Latency
The CAS latency (CL) is the delay, in clock cycles, between the registration of a READ
command and the availability of the first output data. The latency can be set to 2 or 3
clocks, as shown in Figure 27 (page 63).
For CL = 3, if the READ command is registered at clock edge n, then the data will be
nominally available at (n + 2 clocks + tAC). For CL = 2, if the READ command is regis-
tered at clock edge n, then the data will be nominally available at (n + 1 clock + tAC).
2Gb: x16, x32 Mobile LPDDR SDRAM
Standard Mode Register
PDF: 09005aef83a73286
2gb_ddr_mobile_sdram_t69m.pdf - Rev. M 11/10 EN
62
Micron Technology, Inc. reserves the right to change products or specifications without notice.
2009 Micron Technology, Inc. All rights reserved.
相关PDF资料 |
PDF描述 |
|---|---|
| MT46H128M32L4CM-5AT:A | 128M X 32 DDR DRAM, 5 ns, PBGA90 |
| MT46H128M32L4KQ-75:A | 128M X 32 DDR DRAM, 6 ns, PBGA168 |
| MT46H128M32L4MA-54:A | 128M X 32 DDR DRAM, 5 ns, PBGA168 |
| MT46H128M32LFCM-5AT:A | 128M X 32 DDR DRAM, 5 ns, PBGA90 |
| MT46H128M32LFCM-5IT:A | 128M X 32 DDR DRAM, 5 ns, PBGA90 |
相关代理商/技术参数 |
参数描述 |
|---|
发布紧急采购，3分钟左右您将得到回复。