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参数资料
| 型号： | MT46H128M32L2JV-54AT:A |
| 元件分类： | DRAM |
| 英文描述： | 128M X 32 DDR DRAM, 5 ns, PBGA168 |
| 封装： | 12 X 12 MM, GREEN, PLASTIC, VFBGA-168 |
| 文件页数： | 51/106页 |
| 文件大小： | 3431K |
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Figure 21: PRECHARGE Command
CS#
WE#
CAS#
RAS#
CKE
A10
BA0, BA1
HIGH
All banks
Single bank
Bank
CK
CK#
Don’t Care
Address
Note: 1. If A10 is HIGH, bank address becomes “Don’t Care.”
BURST TERMINATE
The BURST TERMINATE command is used to truncate READ bursts with auto pre-
charge disabled. The most recently registered READ command prior to the BURST
TERMINATE command will be truncated, as described in READ Operation (page 69).
The open page from which the READ was terminated remains open.
AUTO REFRESH
AUTO REFRESH is used during normal operation of the device and is analogous to CAS#-
BEFORE-RAS# (CBR) REFRESH in FPM/EDO DRAM. The AUTO REFRESH command is
nonpersistent and must be issued each time a refresh is required.
Addressing is generated by the internal refresh controller. This makes the address bits a
“Don’t Care” during an AUTO REFRESH command.
For improved efficiency in scheduling and switching between tasks, some flexibility in
the absolute refresh interval is provided. The auto refresh period begins when the AU-
TO REFRESH command is registered and ends tRFC later.
2Gb: x16, x32 Mobile LPDDR SDRAM
Commands
PDF: 09005aef83a73286
2gb_ddr_mobile_sdram_t69m.pdf - Rev. M 11/10 EN
49
Micron Technology, Inc. reserves the right to change products or specifications without notice.
2009 Micron Technology, Inc. All rights reserved.
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| MT46H128M32L4KQ-75:A | 128M X 32 DDR DRAM, 6 ns, PBGA168 |
| MT46H128M32L4MA-54:A | 128M X 32 DDR DRAM, 5 ns, PBGA168 |
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