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参数资料
| 型号： | MT46H128M32L2JV-54AT:A |
| 元件分类： | DRAM |
| 英文描述： | 128M X 32 DDR DRAM, 5 ns, PBGA168 |
| 封装： | 12 X 12 MM, GREEN, PLASTIC, VFBGA-168 |
| 文件页数： | 106/106页 |
| 文件大小： | 3431K |
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SELF REFRESH Operation
The SELF REFRESH command can be used to retain data in the device while the rest of
the system is powered down. When in self refresh mode, the device retains data without
external clocking. The SELF REFRESH command is initiated like an AUTO REFRESH
command, except that CKE is disabled (LOW). All command and address input signals
except CKE are “Don’t Care” during self refresh.
During self refresh, the device is refreshed as defined in the extended mode register.
(see Partial-Array Self Refresh (page 65).) An internal temperature sensor adjusts the
refresh rate to optimize device power consumption while ensuring data integrity. (See
The procedure for exiting self refresh requires a sequence of commands. First, CK must
be stable prior to CKE going HIGH. When CKE is HIGH, the device must have NOP com-
mands issued for tXSR to complete any internal refresh already in progress.
During SELF REFRESH operation, refresh intervals are scheduled internally and may
vary. These refresh intervals may differ from the specified tREFI time. For this reason,
the SELF REFRESH command must not be used as a substitute for the AUTO REFRESH
command.
2Gb: x16, x32 Mobile LPDDR SDRAM
SELF REFRESH Operation
PDF: 09005aef83a73286
2gb_ddr_mobile_sdram_t69m.pdf - Rev. M 11/10 EN
99
Micron Technology, Inc. reserves the right to change products or specifications without notice.
2009 Micron Technology, Inc. All rights reserved.
相关PDF资料 |
PDF描述 |
|---|---|
| MT46H128M32L4CM-5AT:A | 128M X 32 DDR DRAM, 5 ns, PBGA90 |
| MT46H128M32L4KQ-75:A | 128M X 32 DDR DRAM, 6 ns, PBGA168 |
| MT46H128M32L4MA-54:A | 128M X 32 DDR DRAM, 5 ns, PBGA168 |
| MT46H128M32LFCM-5AT:A | 128M X 32 DDR DRAM, 5 ns, PBGA90 |
| MT46H128M32LFCM-5IT:A | 128M X 32 DDR DRAM, 5 ns, PBGA90 |
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