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| 型号： | MT46H128M32L2JV-54AT:A |
| 元件分类： | DRAM |
| 英文描述： | 128M X 32 DDR DRAM, 5 ns, PBGA168 |
| 封装： | 12 X 12 MM, GREEN, PLASTIC, VFBGA-168 |
| 文件页数： | 58/106页 |
| 文件大小： | 3431K |
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Table 20: Truth Table – CKE
Notes 1–4 apply to all parameters in this table
Current State
CKEn - 1 CKEn
COMMANDn
ACTIONn
Notes
Active power-down
L
X
Maintain active power-down
Deep power-down
L
X
Maintain deep power-down
Precharge power-down
L
X
Maintain precharge power-down
Self refresh
L
X
Maintain self refresh
Active power-down
L
H
DESELECT or NOP
Exit active power-down
Deep power-down
L
H
DESELECT or NOP
Exit deep power-down
Precharge power-down
L
H
DESELECT or NOP
Exit precharge power-down
Self refresh
L
H
DESELECT or NOP
Exit self refresh
Bank(s) active
H
L
DESELECT or NOP
Active power-down entry
All banks idle
H
L
BURST TERMINATE
Deep power-down entry
All banks idle
H
L
DESELECT or NOP
Precharge power-down entry
All banks idle
H
L
AUTO REFRESH
Self refresh entry
H
H
Notes: 1. CKEn is the logic state of CKE at clock edge n; CKEn - 1 was the state of CKE at the previ-
ous clock edge.
2. Current state is the state of the DDR SDRAM immediately prior to clock edge n.
3. COMMANDn is the command registered at clock edge n, and ACTIONn is a result of COM-
MANDn.
4. All states and sequences not shown are illegal or reserved.
5. DESELECT or NOP commands should be issued on each clock edge occurring during the
tXP or tXSR period.
6. After exiting deep power-down mode, a full DRAM initialization sequence is required.
7. The clock must toggle at least two times during the tXSR period.
2Gb: x16, x32 Mobile LPDDR SDRAM
Truth Tables
PDF: 09005aef83a73286
2gb_ddr_mobile_sdram_t69m.pdf - Rev. M 11/10 EN
55
Micron Technology, Inc. reserves the right to change products or specifications without notice.
2009 Micron Technology, Inc. All rights reserved.
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