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| 型号： | MT46H128M32L2JV-54AT:A |
| 元件分类： | DRAM |
| 英文描述： | 128M X 32 DDR DRAM, 5 ns, PBGA168 |
| 封装： | 12 X 12 MM, GREEN, PLASTIC, VFBGA-168 |
| 文件页数： | 31/106页 |
| 文件大小： | 3431K |
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Table 8: IDD Specifications and Conditions, –40°C to +85°C (x32)
Notes 1–5 apply to all the parameters/conditions in this table; VDD/VDDQ = 1.70–1.95V
Parameter/Condition
Symbol
Max
Unit Notes
-5
-54
-6
-75
Operating 1 bank active precharge current: tRC = tRC (MIN); tCK
= tCK (MIN); CKE is HIGH; CS is HIGH between valid commands;
Address inputs are switching every 2 clock cycles; Data bus in-
puts are stable
IDD0
100
80
70
mA
Precharge power-down standby current: All banks idle; CKE is
LOW; CS is HIGH; tCK = tCK (MIN); Address and control inputs
are switching; Data bus inputs are stable
IDD2P
900
μA
Precharge power-down standby current: Clock stopped; All
banks idle; CKE is LOW; CS is HIGH, CK = LOW, CK# = HIGH; Ad-
dress and control inputs are switching; Data bus inputs are stable
IDD2PS
900
μA
Precharge nonpower-down standby current: All banks idle; CKE
= HIGH; CS = HIGH; tCK = tCK (MIN); Address and control inputs
are switching; Data bus inputs are stable
IDD2N
15
12
mA
Precharge nonpower-down standby current: Clock stopped; All
banks idle; CKE = HIGH; CS = HIGH; CK = LOW, CK# = HIGH; Ad-
dress and control inputs are switching; Data bus inputs are stable
IDD2NS
9
8
mA
Active power-down standby current: 1 bank active; CKE = LOW;
CS = HIGH; tCK = tCK (MIN); Address and control inputs are
switching; Data bus inputs are stable
IDD3P
5
mA
Active power-down standby current: Clock stopped; 1 bank ac-
tive; CKE = LOW; CS = HIGH; CK = LOW; CK# = HIGH; Address
and control inputs are switching; Data bus inputs are stable
IDD3PS
5
mA
Active nonpower-down standby: 1 bank active; CKE = HIGH; CS
= HIGH; tCK = tCK (MIN); Address and control inputs are switch-
ing; Data bus inputs are stable
IDD3N
17
16
15
mA
Active nonpower-down standby: Clock stopped; 1 bank active;
CKE = HIGH; CS = HIGH; CK = LOW; CK# = HIGH; Address and
control inputs are switching; Data bus inputs are stable
IDD3NS
14
13
12
mA
Operating burst read: 1 bank active; BL = 4; CL = 3; tCK = tCK
(MIN); Continuous READ bursts; Iout = 0mA; Address inputs are
switching every 2 clock cycles; 50% data changing each burst
IDD4R
150
145
140
120
mA
Operating burst write: One bank active; BL = 4; tCK = tCK
(MIN); Continuous WRITE bursts; Address inputs are switching;
50% data changing each burst
IDD4W
150
145
140
120
mA
Auto refresh: Burst refresh; CKE = HIGH; Ad-
dress and control inputs are switching; Data
bus inputs are stable
tRFC = 138ns
IDD5
170
mA
tRFC = tREFI
IDD5A
12
mA 10, 11
Deep power-down current: Address and control pins are stable;
Data bus inputs are stable
IDD8
10
μA
2Gb: x16, x32 Mobile LPDDR SDRAM
Electrical Specifications – IDD Parameters
PDF: 09005aef83a73286
2gb_ddr_mobile_sdram_t69m.pdf - Rev. M 11/10 EN
30
Micron Technology, Inc. reserves the right to change products or specifications without notice.
2009 Micron Technology, Inc. All rights reserved.
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