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| 型号： | MT46H128M32L2JV-54AT:A |
| 元件分类： | DRAM |
| 英文描述： | 128M X 32 DDR DRAM, 5 ns, PBGA168 |
| 封装： | 12 X 12 MM, GREEN, PLASTIC, VFBGA-168 |
| 文件页数： | 47/106页 |
| 文件大小： | 3431K |
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Table 17: DM Operation Truth Table
Name (Function)
DM
DQ
Notes
Write enable
L
Valid
Write inhibit
H
X
Notes: 1. Used to mask write data; provided coincident with the corresponding data.
2. All states and sequences not shown are reserved and/or illegal.
DESELECT
The DESELECT function (CS# HIGH) prevents new commands from being executed by
the device. Operations already in progress are not affected.
NO OPERATION
The NO OPERATION (NOP) command is used to instruct the selected device to perform
a NOP. This prevents unwanted commands from being registered during idle or wait
states. Operations already in progress are not affected.
LOAD MODE REGISTER
The mode registers are loaded via inputs A[0:n]. See mode register descriptions in Stand-
MODE REGISTER command can only be issued when all banks are idle, and a subse-
quent executable command cannot be issued until tMRD is met.
ACTIVE
The ACTIVE command is used to activate a row in a particular bank for a subsequent
access. The values on the BA0 and BA1 inputs select the bank, and the address provided
on inputs A[0:n] selects the row. This row remains active for accesses until a PRE-
CHARGE command is issued to that bank. A PRECHARGE command must be issued
before opening a different row in the same bank.
2Gb: x16, x32 Mobile LPDDR SDRAM
Commands
PDF: 09005aef83a73286
2gb_ddr_mobile_sdram_t69m.pdf - Rev. M 11/10 EN
45
Micron Technology, Inc. reserves the right to change products or specifications without notice.
2009 Micron Technology, Inc. All rights reserved.
相关PDF资料 |
PDF描述 |
|---|---|
| MT46H128M32L4CM-5AT:A | 128M X 32 DDR DRAM, 5 ns, PBGA90 |
| MT46H128M32L4KQ-75:A | 128M X 32 DDR DRAM, 6 ns, PBGA168 |
| MT46H128M32L4MA-54:A | 128M X 32 DDR DRAM, 5 ns, PBGA168 |
| MT46H128M32LFCM-5AT:A | 128M X 32 DDR DRAM, 5 ns, PBGA90 |
| MT46H128M32LFCM-5IT:A | 128M X 32 DDR DRAM, 5 ns, PBGA90 |
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