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| 型号： | MT46H128M32L2JV-54AT:A |
| 元件分类： | DRAM |
| 英文描述： | 128M X 32 DDR DRAM, 5 ns, PBGA168 |
| 封装： | 12 X 12 MM, GREEN, PLASTIC, VFBGA-168 |
| 文件页数： | 34/106页 |
| 文件大小： | 3431K |
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Table 11: IDD6 Specifications and Conditions
Notes 1–5, 7, and 12 apply to all the parameters/conditions in this table; VDD/VDDQ = 1.70–1.95V
Parameter/Condition
Symbol
Value
Units
Self refresh:
CKE = LOW; tCK = tCK (MIN); Address and control inputs
are stable; Data bus inputs are stable
Full array, 105C
IDD6
n/a14
μA
Full array, 85C
2000
μA
Full array, 45C
900
μA
1/2 array, 85C
1450
μA
1/2 array, 45C
700
μA
1/4 array, 85C
1230
μA
1/4 array, 45C
600
μA
1/8 array, 85C
1090
μA
1/8 array, 45C
575
μA
1/16 array, 85C
1020
μA
1/16 array, 45C
550
μA
Notes: 1. All voltages referenced to VSS.
2. Tests for IDD characteristics may be conducted at nominal supply voltage levels, but the
related specifications and device operation are guaranteed for the full voltage range
specified.
3. Timing and IDD tests may use a VIL-to-VIH swing of up to 1.5V in the test environment,
but input timing is still referenced to VDDQ/2 (or to the crossing point for CK/CK#). The
output timing reference voltage level is VDDQ/2.
4. IDD is dependent on output loading and cycle rates. Specified values are obtained with
minimum cycle time with the outputs open.
5. IDD specifications are tested after the device is properly initialized and values are aver-
aged at the defined cycle rate.
6. MIN (tRC or tRFC) for IDD measurements is the smallest multiple of tCK that meets the
minimum absolute value for the respective parameter. tRASmax for IDD measurements is
the largest multiple of tCK that meets the maximum absolute value for tRAS.
7. Measurement is taken 500ms after entering into this operating mode to provide settling
time for the tester.
8. VDD must not vary more than 4% if CKE is not active while any bank is active.
9. IDD2N specifies DQ, DQS, and DM to be driven to a valid high or low logic level.
10. CKE must be active (HIGH) during the entire time a REFRESH command is executed.
From the time the AUTO REFRESH command is registered, CKE must be active at each
rising clock edge until tRFC later.
11. This limit is a nominal value and does not result in a fail. CKE is HIGH during REFRESH
command period (tRFC (MIN)) else CKE is LOW (for example, during standby).
12. Values for IDD6 85C are guaranteed for the entire temperature range. All other IDD6 val-
ues are estimated.
13. Typical values at 25C, not a maximum value.
14. Self refresh is not supported for AT (85C to 105C) operation.
2Gb: x16, x32 Mobile LPDDR SDRAM
Electrical Specifications – IDD Parameters
PDF: 09005aef83a73286
2gb_ddr_mobile_sdram_t69m.pdf - Rev. M 11/10 EN
33
Micron Technology, Inc. reserves the right to change products or specifications without notice.
2009 Micron Technology, Inc. All rights reserved.
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