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参数资料
| 型号： | MT46V64M8 |
| 厂商： | Micron Technology, Inc. |
| 英文描述： | 16 Meg x 8 x 4 banks DDR SDRAM(16M x 8 x 4组,双数据速率同步动态RAM) |
| 中文描述： | 16梅格× 8 × 4银行DDR SDRAM内存（1,600 × 8 × 4组，双数据速率同步动态RAM）的 |
| 文件页数： | 17/70页 |
| 文件大小： | 2524K |
| 代理商： | MT46V64M8 |
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17
512Mb: x4, x8, x16 DDR SDRAM
512Mx4x8x16DDR_A.p65
–
Rev. A; Pub 10/00
Micron Technology, Inc., reserves the right to change products or specifications without notice.
2000, Micron Technology, Inc.
512Mb: x4, x8, x16
DDR SDRAM
ADVANCE
REA Ds
READ bursts are initiated with a READ command,
as shown in Figure 6.
The starting column and bank addresses are pro-
vided with the READ command and auto precharge is
either enabled or disabled for that burst access. If auto
precharge is enabled, the row being accessed is
precharged at the completion of the burst. For the
generic READ commands used in the following illus-
trations, auto precharge is disabled.
During READ bursts, the valid data-out element
from the starting column address will be available
following the CAS latency after the READ command.
Each subsequent data-out element will be valid nomi-
nally at the next positive or negative clock edge (i.e., at
the next crossing of CK and CK#). Figure 7 shows
general timing for each possible CAS latency setting.
DQS is driven by the DDR SDRAM along with output
data. The initial LOW state on DQS is known as the
read preamble; the LOW state coincident with the last
data-out element is known as the read postamble.
Upon completion of a burst, assuming no other
commands have been initiated, the DQs will go
High-Z. A detailed explanation of
t
DQSQ (valid data-
out skew),
t
QH (data-out window hold), the valid
data window are depicted in Figure 27. A detailed
explanation of
t
DQSCK (DQS transition skew to CK)
and
t
AC (data-out transition skew to CK) is depicted in
Figure 28.
Data from any READ burst may be concatenated
with or truncated with data from a subsequent READ
command. In either case, a continuous flow of data
can be maintained. The first data element from the new
burst follows either the last element of a completed
burst or the last desired data element of a longer burst
which is being truncated. The new READ command
should be issued
x
cycles after the first READ command,
where
x
equals the number of desired data element
pairs (pairs are required by the 2
n
-prefetch architec-
ture). This is shown in Figure 8. A READ command can
be initiated on any clock cycle following a previous
READ command. Nonconsecutive read data is shown
for illustration in Figure 9. Full-speed random read
accesses within a page (or pages) can be performed as
shown in Figure 10.
Figure 6
READ Command
CS#
WE#
CAS#
RAS#
CKE
CA
x4: A0-A9, A11, A12
x8: A0-A9, A11
x16: A0-A9
A10
BA0,1
HIGH
EN AP
DIS AP
BA
x8: A12
x16: A11, A12
CK
CK#
CA = Column Address
BA = Bank Address
EN AP = Enable Auto Precharge
DIS AP = Disable Auto Precharge
DON
’
T CARE
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