- 您现在的位置：买卖IC网 > PDF目录385639 > MT46V64M8 (Micron Technology, Inc.) 16 Meg x 8 x 4 banks DDR SDRAM(16M x 8 x 4组,双数据速率同步动态RAM) PDF资料下载
参数资料
| 型号： | MT46V64M8 |
| 厂商： | Micron Technology, Inc. |
| 英文描述： | 16 Meg x 8 x 4 banks DDR SDRAM(16M x 8 x 4组,双数据速率同步动态RAM) |
| 中文描述： | 16梅格× 8 × 4银行DDR SDRAM内存（1,600 × 8 × 4组，双数据速率同步动态RAM）的 |
| 文件页数： | 2/70页 |
| 文件大小： | 2524K |
| 代理商： | MT46V64M8 |
第1页当前第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页第39页第40页第41页第42页第43页第44页第45页第46页第47页第48页第49页第50页第51页第52页第53页第54页第55页第56页第57页第58页第59页第60页第61页第62页第63页第64页第65页第66页第67页第68页第69页第70页
2
512Mb: x4, x8, x16 DDR SDRAM
512Mx4x8x16DDR_A.p65
–
Rev. A; Pub 10/00
Micron Technology, Inc., reserves the right to change products or specifications without notice.
2000, Micron Technology, Inc.
512Mb: x4, x8, x16
DDR SDRAM
ADVANCE
GENERAL DESCRIPTION
The 512Mb DDR SDRAM is a high-speed CMOS,
dynamic random-access memory containing
536,870,912 bits. It is internally configured as a quad-
bank DRAM.
The 512Mb DDR SDRAM uses a double data rate
architecture to achieve high-speed operation. The
double data rate architecture is essentially a 2
n
-prefetch
architecture with an interface designed to transfer two
data words per clock cycle at the I/O pins. A single read
or write access for the 512Mb DDR SDRAM effectively
consists of a single 2
n
-bit wide, one-clock-cycle data
transfer at the internal DRAM core and two corre-
sponding
n
-bit wide, one-half-clock-cycle data trans-
fers at the I/O pins.
A bidirectional data strobe (DQS) is transmitted
externally, along with data, for use in data capture at
the receiver. DQS is a strobe transmitted by the DDR
SDRAM during READs and by the memory controller
during WRITEs. DQS is edge-aligned with data for
READs and center-aligned with data for WRITEs. The
x16 offering has two data strobes, one for the lower
byte and one for the upper byte.
The 512Mb DDR SDRAM operates from a differen-
tial clock (CK and CK#); the crossing of CK going HIGH
and CK# going LOW will be referred to as the positive
edge of CK. Commands (address and control signals)
are registered at every positive edge of CK. Input data
is registered on both edges of DQS, and output data is
referenced to both edges of DQS, as well as to both
edges of CK.
Read and write accesses to the DDR SDRAM are
burst oriented; accesses start at a selected location and
continue for a programmed number of locations in a
programmed sequence. Accesses begin with the regis-
tration of an ACTIVE command, which is then fol-
lowed by a READ or WRITE command. The address
bits registered coincident with the ACTIVE command
are used to select the bank and row to be accessed. The
address bits registered coincident with the READ or
WRITE command are used to select the bank and the
starting column location for the burst access.
The DDR SDRAM provides for programmable READ
or WRITE burst lengths of 2, 4, or 8 locations. An auto
precharge function may be enabled to provide a self-
timed row precharge that is initiated at the end of the
burst access.
As with standard SDR SDRAMs, the pipelined,
multibank architecture of DDR SDRAMs allows for
concurrent operation, thereby providing high effective
bandwidth by hiding row precharge and activation
time.
An auto refresh mode is provided, along with a
power-saving power-down mode. All inputs are com-
patible with the JEDEC Standard for SSTL_2. All full
drive strength outputs are SSTL_2, Class II compatible.
NOTE:
1. The functionality and the timing specifications
discussed in this data sheet are for the DLL-enabled
mode of operation.
2. Throughout the data sheet, the various figures and
text refer to DQs as “DQ.” The DQ term is to be
interpreted as any and all DQ collectively, unless
specifically stated otherwise. Additionally, the x16
is divided in to two bytes—the lower byte and upper
byte. For the lower byte (DQ0 through DQ7) DM
refers to LDM and DQS refers to LDQS; and for the
upper byte (DQ8 through DQ15) DM refers to UDM
and DQS refers to UDQS.
(Note: xx= 7, 75, or 8)
256Mb DDR SDRAM PART NUMBERS
PART NUMBER
MT46V128M4TH-xx
MT46V128M4TH-xxL
CONFIGURATION
128 Meg x 4
128 Meg x 4
I/O DRIVE LEVEL
Full Drive
Full Drive
REFRESH OPTION
Standard
Low Power
PACKAGE
66-pin TSOP (27mm)
66-pin TSOP (27mm)
MT46V64M8TH-xx
MT46V64M8TH-xxL
64 Meg x 8
64 Meg x 8
Full Drive
Full Drive
Standard
Low Power
66-pin TSOP (27mm)
66-pin TSOP (27mm)
MT46V32M16D1TH-xx
MT46V32M16D1TH-xxL
MT46V32M16D2TH-xx
MT46V32M16D2TH-xxL
MT46V32M16D3TH-xx
MT46V32M16D3TH-xxL
32 Meg x 16
32 Meg x 16
32 Meg x 16
32 Meg x 16
32 Meg x 16
32 Meg x 16
Full Drive
Full Drive
Reduced Drive
Reduced Drive
Programmable Drive
Programmable Drive
Standard
Low Power
Standard
Low Power
Standard
Low Power
66-pin TSOP (27mm)
66-pin TSOP (27mm)
66-pin TSOP (27mm)
66-pin TSOP (27mm)
66-pin TSOP (27mm)
66-pin TSOP (27mm)
相关PDF资料 |
PDF描述 |
|---|---|
| MT48LC16M8A1TG | SYNCHRONOUS DRAM |
| MT48LC32M4A1 | ECONOLINE: RSZ/P - 1kVDC |
| MT48LC32M4A2 | SYNCHRONOUS DRAM |
| MT48LC32M4A1TG | SYNCHRONOUS DRAM |
| MT48LC8M16A1TG | SYNCHRONOUS DRAM |
相关代理商/技术参数 |
参数描述 |
|---|
发布紧急采购，3分钟左右您将得到回复。