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参数资料
| 型号： | MT46V64M8 |
| 厂商： | Micron Technology, Inc. |
| 英文描述： | 16 Meg x 8 x 4 banks DDR SDRAM(16M x 8 x 4组,双数据速率同步动态RAM) |
| 中文描述： | 16梅格× 8 × 4银行DDR SDRAM内存（1,600 × 8 × 4组，双数据速率同步动态RAM）的 |
| 文件页数： | 47/70页 |
| 文件大小： | 2524K |
| 代理商： | MT46V64M8 |
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47
512Mb: x4, x8, x16 DDR SDRAM
512Mx4x8x16DDR_A.p65
–
Rev. A; Pub 10/00
Micron Technology, Inc., reserves the right to change products or specifications without notice.
2000, Micron Technology, Inc.
512Mb: x4, x8, x16
DDR SDRAM
ADVANCE
I
DD
SPECIFICATIONS AND CONDITIONS (x16)
(Notes: 1
–
5, 10, 12, 14; notes appear on pages 50
–
53) (0
°
C
≤
T
A
≤
+70
°
C; V
DD
Q = +2.5V ±0.2V, V
DD
= +2.5V ±0.2V)
PARAMETER/CONDITION
OPERATING CURRENT: One bank; Active-Precharge;
t
RC =
t
RC
(MIN)
;
t
CK =
t
CK
(MIN)
; DQ, DM, and DQS inputs changing once per clock
cyle; Address and control inputs changing once every two clock cycles;
OPERATING CURRENT: One bank; Active-Read-Precharge;
Burst = 2;
t
RC =
t
RC(MIN);
t
CK =
t
CK(MIN); I
OUT
= 0mA;
Address and control inputs changing once per clock cycle
PRECHARGE POWER-DOWN STANDBY CURRENT: All banks idle;
Power-down mode;
t
CK =
t
CK(MIN); CKE = LOW;
IDLE STANDBY CURRENT: CS# = HIGH; All banks idle;
t
CK =
t
CK
(MIN)
;
CKE = HIGH; Address and other control inputs changing once per
clock cycle.
V
IN
=
V
REF
for DQ, DQS, and DM
ACTIVE POWER-DOWN STANDBY CURRENT: One bank active;
Power-down mode;
t
CK =
t
CK(MIN); CKE = LOW
ACTIVE STANDBY CURRENT: CS# = HIGH; CKE = HIGH;
One bank; Active-Precharge;
t
RC =
t
RAS(MAX);
t
CK =
t
CK(MIN);
DQ, DM, and DQS inputs changing twice per clock cycle; Address
and other control inputs changing once per clock cycle
OPERATING CURRENT: Burst = 2; Reads; Continuous burst;
One bank active; Address and control inputs changing once per
clock cycle;
t
CK =
t
CK(MIN); I
OUT
= 0mA
OPERATING CURRENT: Burst = 2; Writes; Continuous burst;
One bank active; Address and control inputs changing once per
clock cycle;
t
CK =
t
CK(MIN); DQ, DM, and DQS inputs
changing twice per clock cycle
AUTO REFRESH CURRENT
SYMBOL
I
DD
0
-7
-75
TBD
-8
UNITS NOTES
mA
TBD
TBD
22, 48
I
DD
1
TBD
TBD
TBD
mA
22, 48
I
DD
2P
3
3
3
mA
23, 32
50
51
I
DD
2F
40
40
35
mA
I
DD
3P
3
3
3
mA
50
mA
23, 32
I
DD
3N
35
35
30
22
I
DD
4R
TBD
TBD
TBD
mA
22, 48
I
DD
4W
TBD
TBD
TBD
mA
22
t
RC =
t
RFC(MIN)
t
RC =
7.8125μs
Standard
Low power (L)
I
DD
5
I
DD
6
I
DD
7
I
DD
7
I
DD
8
TBD
6
TBD
TBD
TBD
TBD
6
TBD
TBD
TBD
TBD
6
TBD
TBD
TBD
mA
mA
mA
mA
mA
22,50
27,50
11
11
22, 49
SELF REFRESH CURRENT: CKE
≤
0.2V
OPERATING CURRENT: Four bank interleaving READs (BL=4) with
auto precharge with ,
t
RC =
t
RC
(MIN)
;
t
CK =
t
RC
(MIN)
; Address and
control inputs change only during Active READ, or WRITE commands.
MA X
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