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| 型号： | MTA85812S-10I/SS |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 8-BIT, OTPROM, 10 MHz, RISC MICROCONTROLLER, PDSO20 |
| 封装： | 0.209 INCH, PLASTIC, SSOP-20 |
| 文件页数： | 16/72页 |
| 文件大小： | 760K |
| 代理商： | MTA85812S-10I/SS |
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1995 Microchip Technology Inc.
DS40115C-page 23
MTA85XXX
10.0
WATCHDOG TIMER (WDT)
The watchdog timer is realized as a free running on-
chip RC oscillator which does not require any external
components. This RC oscillator is separate from the
RC oscillator of the OSC1/CLKIN pin. That means that
the WDT will run even if the clock on the OSC1/CLKIN
and OSC2/CLKOUT pins of the device have been
stopped (i.e., by executing the SLEEP instruction).
During normal operation a WDT time-out generates a
device RESET. If the device is in SLEEP mode, a WDT
time-out causes the device to wake-up and continue
with normal operation. The WDT can be permanently
disabled by programming the configuration bit WDTE
as a '0'.
10.1
WDT Period
The WDT has a nominal time-out period of 18 ms, (with
no prescaler). These periods vary with temperature,
VDD and process variations from part to part (see DC
specifications). If longer time-out periods are desired, a
prescaler with a division ratio of up to 1:128 can be
assigned to the WDT (under software control) by
writing to the OPTION register. Thus, time-out periods
up to 2.3 seconds can be realized.
The CLRWDT and SLEEP instructions clear the WDT
and the postscaler (if assigned to the WDT) and pre-
vent it from timing out and generating a device RESET.
The TO bit (STATUS<4>) will be cleared upon a WDT
time-out.
10.2
WDT Programming Considerations
At worst case conditions (VDD = Min., Temperature =
Max., max. WDT prescaler) it may take several
seconds before a WDT time-out occurs.
FIGURE 10-1: WATCHDOG TIMER BLOCK DIAGRAM
TABLE 10-1:
SUMMARY OF REGISTERS ASSOCIATED WITH THE WATCHDOG TIMER
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Config. Word
CP
WDTE
FOSC1
FOSC0
OPTION
—
T0CS
T0SE
PSA
PS2
PS1
PS0
Note 1: CP7:CP4 are used by the PIC16CCR58A only. Unused in all other devices.
2: Shaded cells are not used by the Watchdog Timer.
1
0
1
0
From TMR0 Clock Source
(Figure 6-6)
To TMR0 (Figure 6-6)
Postscaler
Note: PSA and PS2:PS0 are bits in the OPTION register.
WDT Enable
EPROM Fuse
PSA
WDT
Time-out
PS2:PS0
PSA
MUX
8 - to - 1 MUX
Postscaler
M
U
X
Watchdog
Timer
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