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| 型号： | MTA85812S-10I/SS |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 8-BIT, OTPROM, 10 MHz, RISC MICROCONTROLLER, PDSO20 |
| 封装： | 0.209 INCH, PLASTIC, SSOP-20 |
| 文件页数： | 4/72页 |
| 文件大小： | 760K |
| 代理商： | MTA85812S-10I/SS |
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MTA85XXX
DS40115C-page 12
1995 Microchip Technology Inc.
5.2
Indirect Data Addressing (INDF) f0
This
is
not
a
physically
implemented
register.
Addressing INDF calls for the contents of the File
Select Register to be used to select a file register. The
INDF register is useful as an indirect address pointer.
For example, in the instruction ADDWF INDF, W will
add the contents of the register pointed to by the FSR
to the content of the W Register and place the result in
W.
If INDF itself is read through indirect addressing
(i.e., FSR = 0h), then 00h is read. If the INDF register
is written to via indirect addressing, the result will be a
no operation (NOP).
5.3
Real Time Clock/Counter Register
(T0CKI) f1
This register can be loaded and read by the program as
any other register. In addition, its contents can be
incremented by an external signal edge applied to the
T0CKI pin or by the internal instruction cycle clock
(CLKOUT = FOSC/4). Figure 5-2 is a simplified block
diagram of the T0CKI module.
An 8-bit prescaler can be assigned to the T0CKI by
writing the proper values to the PSA bit and the PS bits
in the OPTION register. The OPTION register is a
special
register
(not
mapped
in
data
memory)
addressable
using
the
OPTION
instruction
(Section 6.4). If the prescaler is assigned to the T0CKI,
instructions writing to the T0CKI register (e.g., CLRF
T0CKI
, or BSF T0CKI,5,...etc.) clear the prescaler.
The bit RTS (T0CKI Signal Source) in the OPTION
register determines if the T0CKI register is incremented
internally or externally.
RTS = 1: The clock source for the T0CKI or the
prescaler, if assigned to it, is the signal on the T0CKI
pin. Bit4 of the OPTION register (RTE) determines if an
increment occurs on the falling (RTE = 1) or rising
(RTE = 0) edge of the signal presented to the T0CKI
pin.
RTS = 0: The T0CKI register or its prescaler,
respectively, will be incremented with the internal
instruction clock (= FOSC/4). The RTE bit in the
OPTION register and the T0CKI pin are "don't care" in
this case. However, the T0CKI pin must not be left
floating (tie to VDD or VSS). This prevents unintended
operation and to reduce the current consumption in
low-power applications.
As long as clocks are applied to the T0CKI (from
internal or external source, with or without prescaler),
the T0CKI register keeps incrementing and just rolls
over when the value FFh is reached. All increment
pulses for the T0CKI register are delayed by two
instruction cycles. After writing to the T0CKI register,
for example, no increment takes place for the following
two instruction cycles. This is independent if internal or
external clock source is selected. If a prescaler is
assigned to the T0CKI, the output of the prescaler will
be delayed by two cycles before the T0CKI register is
incremented. This is true for instructions that either
write to or read-modify-write T0CKI (e.g., MOVF
T0CKI, CLRF T0CKI
). For applications where T0CKI
needs to be tested for '0' without affecting its count, use
of the MOVF T0CKI, W instruction is recommended.
Timing diagrams in Figure 5-3 and Figure 5-4 show
T0CKI read, write and increment timing.
5.3.1
USING T0CKI WITH EXTERNAL CLOCK
When external clock input is used for T0CKI, it is
synchronized with internal phase clocks. Therefore,
external clock input must meet certain requirements.
Also there is some delay from the occurrence of the
external clock edge to the actual incrementing of
T0CKI. Referring to Figure 5-5, the synchronization is
done after the prescaler. Output of the prescaler is
sampled twice in every instruction cycle to detect rising
or falling edges. Therefore, it is necessary for PSOUT
to be high for at least 2 TOST and low for at least 2 TOSC
where:
TOSC = oscillator time period.
When no prescaler is used, PSOUT (Prescaler output,
Figure 5-3) is the same as T0CKI clock input and,
therefore, the requirements are:
TRTH
=
T0CKI high time
≥ 2 TOSC + 20 ns
TRTL
=
T0CKI low time
≥ 2 TOSC + 20 ns
When prescaler is used, the T0CKI input is divided by
the asynchronous ripple counter-type prescaler so the
prescaler output is symmetrical.
Then:
PSOUT high time = PSOUT low time =
where TRT = T0CKI input period and N = prescale value
(2, 4, ...., 256).
The requirement is, therefore,
≥ 2 TOSC + 20 ns, or
The user will notice that no requirement on T0CKI high
time or low time is specified. However, if the high time
or low time on T0CKI is too small, then the pulse may
not be detected. Hence, a minimum high or low time of
10 ns is required. In summary, the T0CKI input
requirements are:
TRT
=
T0CKI period
≥ (4 TOSC + 40 ns)/N
TRTH
=
T0CKI high time
≥ 10 ns
TRTL
=
T0CKI low time
≥ 10 ns
Delay from external clock edge: Since the prescaler
output is synchronized with the internal clocks, there is
a small delay from the time the external clock edge
occurs to the time the T0CKI is actually incremented.
This delay is between 3 TOSC and 7 TOSC (Figure 5-5).
Thus, for example, measuring the interval between two
edges (e.g., period) will be accurate within
±4 TOSC
(
±200 ns @ 20 MHz).
N
TRT
2
N
TRT
2
4 TOSC + 40 ns
N
TRT
≥
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