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| 型号： | MTA85812S-10I/SS |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 8-BIT, OTPROM, 10 MHz, RISC MICROCONTROLLER, PDSO20 |
| 封装： | 0.209 INCH, PLASTIC, SSOP-20 |
| 文件页数： | 24/72页 |
| 文件大小： | 760K |
| 代理商： | MTA85812S-10I/SS |
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MTA85XXX
DS40115C-page 30
1995 Microchip Technology Inc.
13.0
POWER-DOWN MODE (SLEEP)
The Power-Down mode is entered by executing a
SLEEP
instruction.
If enabled, the Watchdog Timer will be cleared but
keeps running, the TO bit (STATUS<4>) is set, the PD
bit (STATUS<3>) is cleared, and the oscillator driver is
turned off. The I/O ports maintain the status they had
before the SLEEP instruction was executed (driving
high, driving low, or hi-impedance).
It should be noted that a RESET generated by a WDT
time-out does not drive the MCLR/VPP pin low.
For lowest current consumption while powered down,
the T0CKI input should be at VDD or VSS and the
MCLR/VPP pin must be at a logic high level (VIHMC).
13.0.1
WAKE-UP FROM SLEEP
The device can wake from SLEEP through one of the
following events:
1.
An external reset input on the MCLR/VPP pin.
2.
A WDT time-out reset (if WDT was enabled).
Both of these events cause a device reset. The TO and
PD bits can be used to determine the cause of device
reset. The TO bit is cleared if a WDT time-out occurred
(and caused wake-up). The PD bit, which is set on
power-up, is cleared when SLEEP is invoked.
The WDT is cleared when the device wakes from
SLEEP, regardless of the wake-up source.
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